Patents by Inventor Seung-yong Cha
Seung-yong Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240119994Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
-
Patent number: 11837577Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: GrantFiled: June 29, 2022Date of Patent: December 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Nee Jang, Kyung Suk Oh, Eunseok Song, Seung-Yong Cha
-
Publication number: 20220328454Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-Nee JANG, Kyung Suk OH, Eunseok SONG, Seung-Yong CHA
-
Patent number: 11398454Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: GrantFiled: May 26, 2020Date of Patent: July 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-Nee Jang, Kyung Suk Oh, Eunseok Song, Seung-Yong Cha
-
Patent number: 11244938Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.Type: GrantFiled: August 29, 2019Date of Patent: February 8, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Choi, Eun-Seok Song, Seung-Yong Cha, Yun-Hee Lee
-
Publication number: 20210118848Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.Type: ApplicationFiled: May 26, 2020Publication date: April 22, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ae-Nee JANG, Kyung Suk OH, Eunseok SONG, Seung-Yong CHA
-
Patent number: 10879294Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.Type: GrantFiled: December 4, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-hoon Kim, Ji-chul Kim, Seung-yong Cha, Jae-choon Kim
-
Publication number: 20200135790Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.Type: ApplicationFiled: December 4, 2019Publication date: April 30, 2020Inventors: Yong-hoon KIM, Ji-chul KIM, Seung-yong CHA, Jae-choon KIM
-
Patent number: 10541263Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.Type: GrantFiled: October 30, 2017Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-hoon Kim, Ji-chul Kim, Seung-yong Cha, Jae-choon Kim
-
Publication number: 20190385997Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: JU-YOUN CHOI, EUN-SEOK SONG, SEUNG-YONG CHA, YUN-HEE LEE
-
Patent number: 10424571Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.Type: GrantFiled: September 6, 2017Date of Patent: September 24, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Youn Choi, Eun-Seok Song, Seung-Yong Cha, Yun-Hee Lee
-
Patent number: 10037938Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.Type: GrantFiled: April 27, 2017Date of Patent: July 31, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Keung Beum Kim, Hyunjong Moon, Seung-Yong Cha
-
Publication number: 20180190635Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.Type: ApplicationFiled: September 6, 2017Publication date: July 5, 2018Inventors: JU-YOUN CHOI, EUN-SEOK SONG, SEUNG-YONG CHA, YUN-HEE LEE
-
Publication number: 20180138225Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.Type: ApplicationFiled: October 30, 2017Publication date: May 17, 2018Inventors: Yong-hoon KIM, Ji-chul KIM, Seung-yong CHA, Jae-choon KIM
-
Publication number: 20180122772Abstract: A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.Type: ApplicationFiled: April 27, 2017Publication date: May 3, 2018Inventors: KEUNG BEUM KIM, HYUNJONG MOON, SEUNG-YONG CHA
-
Patent number: 9830973Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.Type: GrantFiled: June 30, 2017Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Keung Beum Kim, HyunJong Moon, Heeseok Lee, Seung-Yong Cha
-
Patent number: 9799591Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.Type: GrantFiled: August 13, 2015Date of Patent: October 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Yong Cha, Keung Beum Kim, Yonghoon Kim, HyunJong Moon, Heeseok Lee
-
Publication number: 20170301392Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.Type: ApplicationFiled: June 30, 2017Publication date: October 19, 2017Inventors: Keung Beum Kim, HyunJong Moon, Heeseok Lee, Seung-Yong Cha
-
Patent number: 9721644Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.Type: GrantFiled: July 12, 2016Date of Patent: August 1, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Keung Beum Kim, HyunJong Moon, Heeseok Lee, Seung-Yong Cha
-
Patent number: 9659852Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.Type: GrantFiled: December 2, 2015Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tongsuk Kim, HyunJong Moon, Tai-Hyun Eum, Heeseok Lee, Keung Beum Kim, Yonghoon Kim, Yoonha Jung, Seung-Yong Cha