Abstract: The disclosure discloses anti ?-Syn antibodies preferentially recognizing ?-Syn aggregates. The antibodies of the present invention bind to ?-Syn aggregates with high affinity and specificity and inhibit accumulation or intercellular transfer of ?-Syn aggregates, and thus can be used for detection, diagnosis and/or treatment or prevention of various diseases caused by the accumulation of ?-Syn aggregates.

Abstract: The present disclosure includes a negative active material manufacturing method for lithium secondary battery, comprising: grinding the metal-based material into metal-based material nanoparticles through a grinding process; obtaining spherical particles by spheronizing the pulverized metal-based material nanoparticle, a conductive material, and a conductive additive together; obtaining a composite by complexing the spherical particles with an amorphous carbon-based precursor material; and carbonizing the composite; the conductive additive is a carbon nanotube; a content of the carbon nanotube is 0.2 to 2.3 wt % compared to the metal-based material nanoparticle in the composite, a negative active material according to the method, and a secondary battery including the same.

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Abstract: A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.

Abstract: The present invention relates, in general, to a method of conveniently making up a character string in smart phone-based messengers or Internet-based Social Network Services (SNSs) by utilizing technology for implementing a user-friendly interface using multi-touch, a gyro sensor, etc.

Abstract: A hairdressing device includes a pair of arm members opposed to each other and hingedly connected at one longitudinal ends thereof, each of the arm members including a hinge portion, a grip portion contiguous to the hinge portion and a hair-pinching portion contiguous to the grip portion; and a heater member arranged in the hair-pinching portion of each of the arm members to generate heat when supplied with electric power. The heater member includes a pair of heating plates arranged side by side in a spaced-apart relationship with each other. The heater member includes a heat-resistant transparent member arranged between the heating plates to transmit infrared rays.

Abstract: A hairdressing device includes a pair of arm members opposed to each other and hingedly connected at one longitudinal ends thereof, each of the arm members including a hinge portion, a grip portion contiguous to the hinge portion and a hair-pinching portion contiguous to the grip portion; and a heater member arranged in the hair-pinching portion of each of the arm members to generate heat when supplied with electric power. The heater member includes a pair of heating plates arranged side by side in a spaced-apart relationship with each other. The heater member includes a heat-resistant transparent member arranged between the heating plates to transmit infrared rays.

Abstract: A clock transmission apparatus for network synchronization between systems wherein a communication system having a main unit and a remote unit, the main unit generates an even-second (PP2S) pulse and transmits it to the remote unit and the remote unit uses the received PP2S to generate a system clock and a 10 MHz clock, so that network synchronization is realized between two systems. Network synchronization can be maintained between two systems using a cheap UTP (Unshielded Twisted Pair) without using a GPS system and an expensive transmission line.

Abstract: This invention is about a Ceramic Heater which comprises a built-in heating unit circuit and a built-in separate temperature sensor circuit, wherein precision circuit printing technology and layering technology are used, and which is manufactured by means of cofiring process. This invention is featured by a first circuit board, a heating circuit in certain patterns on the top side of the aforesaid first board, a sensor circuit positioned between the patterns of the heating circuit, and a second board which is layered over the aforesaid first board.

Abstract: Securing a heat sink to an electronic device, such as an integrated circuit package, includes applying an adhesive layer to only a periphery of a surface on a thermal interface material. The thermal interface material is applied to the heat sink and/or integrated circuit package using the adhesive layer. The heat sink is in thermal contact with the integrated circuit package to extract heat during operation.