Patents by Inventor Seungbae Park
Seungbae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11663081Abstract: A storage system caches, in volatile memory, data read from non-volatile memory. After detecting an uncorrectable error in the data cached in the volatile memory, the storage system replaces the cached data with data re-read from the non-volatile memory and updated to reflect any changes made to the data after it was stored in the non-volatile memory. The storage system can also analyze a pattern in data adjacent to the uncorrectable error and predict corrected data based on the pattern.Type: GrantFiled: May 10, 2021Date of Patent: May 30, 2023Assignee: Western Digital Technologies, Inc.Inventors: Seungbae Park, Minyoung Kim, Minwoo Lee, Namjung Hwang
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Publication number: 20220358016Abstract: A storage system caches, in volatile memory, data read from non-volatile memory. After detecting an uncorrectable error in the data cached in the volatile memory, the storage system replaces the cached data with data re-read from the non-volatile memory and updated to reflect any changes made to the data after it was stored in the non-volatile memory. The storage system can also analyze a pattern in data adjacent to the uncorrectable error and predict corrected data based on the pattern.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Applicant: Western Digital Technologies, Inc.Inventors: Seungbae Park, Minyoung Kim, Minwoo Lee, Namjung Hwang
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Patent number: 10222209Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.Type: GrantFiled: January 4, 2018Date of Patent: March 5, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Seungbae Park, Yu-Ho Hsu, Chin-Li Kao, Tai-Yuan Huang
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Publication number: 20180128612Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.Type: ApplicationFiled: January 4, 2018Publication date: May 10, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Seungbae Park, Yu-Ho Hsu, Chin-Li Kao, Tai-Yuan Huang
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Patent number: 9891048Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.Type: GrantFiled: January 29, 2014Date of Patent: February 13, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Seungbae Park, Yu-Ho Hsu, Chin-Li Kao, Tai-Yuan Huang
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Publication number: 20150211852Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.Type: ApplicationFiled: January 29, 2014Publication date: July 30, 2015Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Seungbae PARK, Yu-Ho HSU, Chin-Li KAO, Tai-Yuan HUANG
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Publication number: 20120018084Abstract: Disclosed herein is a printed circuit board assembly manufacturing device and method of manufacturing a printed circuit board assembly. The printed circuit board assembly manufacturing device may include a fusing unit configured to cure a conductive adhesive used to fix electronic components having different heights to a printed circuit board. The fusing unit may be configured to cure the conductive adhesive while simultaneously applying pressure to the electronic components having different heights.Type: ApplicationFiled: July 6, 2011Publication date: January 26, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Woon Jang, Seungbae Park, Young Jun Moon, Soon Min Hong, Chang-kyu Chung, Dae Jung Kim, Sang il Hong
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Publication number: 20080119029Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.Type: ApplicationFiled: January 17, 2008Publication date: May 22, 2008Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
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Patent number: 7348261Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.Type: GrantFiled: May 15, 2003Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
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Publication number: 20080029888Abstract: A method and article of fabrication is described featuring a solder layer having a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path along which the crack propagates.Type: ApplicationFiled: December 14, 2006Publication date: February 7, 2008Applicant: International Business Machines CorporationInventors: Seungbae Park, Sanjeev Sathe, Aleksander Zubelewicz
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Publication number: 20030199121Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.Type: ApplicationFiled: May 15, 2003Publication date: October 23, 2003Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
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Patent number: 6627998Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.Type: GrantFiled: July 27, 2000Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
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Patent number: 6347901Abstract: A method and article of fabrication is described featuring a solder layer having a serpentine, interrupted, or interdigitated boundary. The non-planar design of the boundary layer increases the fatigue life of the solder joint by limiting the damage caused by micro-cracking. This irregularity of the solder boundary constrains the propagation of cracks by creating obstacles along the crack path, redirecting the crack away from the intermetallic layer, or by increasing the path along which the crack propagates.Type: GrantFiled: November 1, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Seungbae Park, Sanjeev Sathe, Aleksander Zubelewicz
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Patent number: 6291776Abstract: A chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, disclosed is a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the uniformly, equidistant positioning of metal-plated through-holes (PTH) formed in the chip carrier relative to contact pads. A plurality of plated through-holes (PTH) are positioned equidistantly relative to contact (BGA) pads on a surface of a substrate which is constituted of an organic laminate material, so as to be able to control both in-plane and out-of-plane thermal deformations in the chip carrier material which may be occasioned in a solder reflow furnace or oven.Type: GrantFiled: November 3, 1998Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Voya R. Markovich, Peter A. Moschak, Seungbae Park, Sanjeev B. Sathe
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Patent number: 6288900Abstract: A heat spreading cap is placed over a chip or integrated circuit. The cap is shaped or sized to provide a distinct heat spreading and/or stiffness characteristic that differs as it extends into different regions of the module. The areas of differing stiffness or CTE reduce the warpage (or bending) of the module, thereby reducing the overall stress in the BGA.Type: GrantFiled: December 2, 1999Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: Eric A. Johnson, Seungbae Park