Patents by Inventor Seungbin Baek

Seungbin Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237241
    Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanggyoo Jung, Seungbin Baek, Hyunjung Song, Jisun Yang
  • Publication number: 20240079349
    Abstract: A semiconductor package is provided to include a package substrate, a plurality of semiconductor chips mounted on the package substrate, an interposer arranged between the package substrate and the plurality of semiconductor chips, a plurality of passive elements mounted on the package substrate and spaced apart from the interposer, a first stiffener positioned on the package substrate and including a first hole accommodating the interposer and a second hole accommodating the plurality of passive elements, and a second stiffener positioned on the first stiffener and including a third hole communicating with the first hole. The first stiffener has a first coefficient of thermal expansion, and the second stiffener has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.
    Type: Application
    Filed: June 14, 2023
    Publication date: March 7, 2024
    Inventors: Yanggyoo Jung, Younglyong Kim, Seungbin Baek
  • Publication number: 20230011941
    Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.
    Type: Application
    Filed: April 12, 2022
    Publication date: January 12, 2023
    Inventors: Yanggyoo JUNG, Seungbin BAEK, Hyunjung SONG, Jisun YANG
  • Publication number: 20220415772
    Abstract: Provided is a semiconductor package including a first wiring pad on a package substrate; a first wiring connection part on the first wiring pad and including a wiring solder layer; a second wiring pad on the package substrate; a second wiring connection part on the second wiring pad and including a conductor; an interposer substrate on the first wiring connection part and the second wiring connection part, wherein a first substrate connection part and a second substrate connection part respectively electrically connected to the first wiring connection part and the second wiring connection part are arranged on a rear surface of the interposer substrate; and semiconductor chips apart from each other in a two-dimensional manner on the interposer substrate, wherein each of the semiconductor chips is electrically connected to the interposer substrate via a chip connection pillar.
    Type: Application
    Filed: February 17, 2022
    Publication date: December 29, 2022
    Inventors: Yanggyoo Jung, Seungbin Baek, Hyunjung Song, Sangmin Yong