Abstract: A semiconductor device including cell array and peripheral circuit regions; a peripheral gate structure including a peripheral gate electrode on a peripheral gate dielectric, peripheral source/drains on sides of the gate electrode, and a peripheral gate capping pattern on the peripheral gate electrode; a first peripheral interlayer insulating layer on sides of the peripheral gate structure; peripheral interconnections on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer on the peripheral interconnections; a connection structure including a pad pattern, and a first peripheral contact plug penetrating the insulating pattern layer and electrically connecting the peripheral interconnections to the pad pattern; and a guard ring structure surrounding the cell array region between the cell array and the peripheral circuit regions. A portion of a guard ring of the guard ring structure is at a same level as a portion of the first peripheral contact plug.

Abstract: Provided is an integrated circuit device including a substrate having a cell array area, a peripheral circuit area surrounding the cell array area, and an interface area between the cell array area and the peripheral circuit area, a plurality of bit lines extending in a first horizontal direction on the cell array area and the interface area and placed parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, insulating capping patterns extending in the first horizontal direction on the bit lines, a plurality of contact plugs vertically connected to the bit lines, respectively, in the interface area, and a plurality of contact pads disposed on the plurality of contact plugs, respectively, wherein the contact plugs are spaced apart from centers of the bit lines in the second horizontal direction at a certain gap in the second horizontal direction.

Abstract: A semiconductor device may include first and second bit lines that each include a line portion, a connection portion extending from the line portion into a first extension region, and a pad portion extending from the connection portion in the first extension region; and a third bit line between the line portions of the first and second bit lines in a memory cell array region and the first extension region. A first end portion of the third bit line may be in the first extension region. The pad portions of the first and second bit lines each may be wider than the line portions of the first and second bit lines. A minimum distance between the pad portions of the first and second bit lines may be less than a minimum distance between the line portion of the first bit line and the third bit line.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the substrate, the gate structure extending across the active region in a first horizontal direction, bit line structures on bit line trenches extending in a second horizontal direction, intersecting the first horizontal direction, the bit line trenches on an upper surface of the substrate across the gate structure, contact plugs between the bit line structures, landing pad structures on the contact plugs, and an insulating pattern between the landing pad structures, the insulating pattern in contact with the bit line structures. Portions of the bit line structures extend in the second horizontal direction in the bit line trenches. Each of the landing pad structures includes a lower landing pad, arranged on a level lower than that of each of upper surfaces of the bit line structures, and an upper landing pad on the lower landing pad.

Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.

Abstract: A semiconductor device includes a first contact structure on a central portion of the active pattern, a bit line structure on the first contact structure, a spacer structure on sidewalls of the bit line structure and the first contact structure and including a first spacer, a second spacer, an etch stop pattern and a third spacer sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate, a second contact structure on an end portion of the active pattern, and a capacitor on the second contact structure. A lowermost surface of the first spacer may be lower than a lowermost surface of the second spacer, and lower surfaces of the etch stop pattern and the third spacer may be higher than the lowermost surface of the second spacer.

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.