Patents by Inventor Seung Geun Baek
Seung Geun Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11943976Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.Type: GrantFiled: June 4, 2020Date of Patent: March 26, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seung Sok Son, Woo Geun Lee, Seul Ki Kim, Kap Soo Yoon, Hyun Woong Baek, Jae Hyun Lee, Su Jung Jung, Jung Kyoung Cho, Seung Ha Choi, June Whan Choi
-
Publication number: 20230298631Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.Type: ApplicationFiled: August 10, 2022Publication date: September 21, 2023Inventors: Jae Hyung PARK, Seung Geun BAEK, Dong Uk LEE
-
Patent number: 10055152Abstract: A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.Type: GrantFiled: May 25, 2017Date of Patent: August 21, 2018Assignee: SK hynix Inc.Inventors: Seung Geun Baek, Jin Hee Cho
-
Patent number: 10003323Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.Type: GrantFiled: September 6, 2017Date of Patent: June 19, 2018Assignee: SK hynix Inc.Inventors: Seung Geun Baek, Jae Il Kim
-
Publication number: 20180165024Abstract: A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.Type: ApplicationFiled: May 25, 2017Publication date: June 14, 2018Applicant: SK hynix Inc.Inventors: Seung Geun BAEK, Jin Hee CHO
-
Publication number: 20170366169Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.Type: ApplicationFiled: September 6, 2017Publication date: December 21, 2017Applicant: SK hynix Inc.Inventors: Seung Geun BAEK, Jae Il KIM
-
Patent number: 9787287Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.Type: GrantFiled: January 18, 2017Date of Patent: October 10, 2017Assignee: SK hynix Inc.Inventors: Seung Geun Baek, Jae Il Kim
-
Patent number: 9747984Abstract: A semiconductor device may include a ZQ calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The ZQ calibration circuit may perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. The reference code generating circuit may output a predetermined code value as a reference code. The variable information generating circuit may compare the ZQ calibration code to the reference code to generate variable information. The internal circuit may determine operation timings based on a difference between the ZQ calibration code and the reference code.Type: GrantFiled: February 22, 2016Date of Patent: August 29, 2017Assignee: SK hynix Inc.Inventors: Seung Geun Baek, Jae Il Kim
-
Publication number: 20170134006Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.Type: ApplicationFiled: January 18, 2017Publication date: May 11, 2017Inventors: Seung Geun BAEK, Jae Il KIM
-
Publication number: 20170062050Abstract: A semiconductor device may include a ZQ calibration circuit, a reference code setting circuit, a variable information generating circuit, and an internal circuit. The ZQ calibration circuit may perform a ZQ calibration operation in response to a ZQ calibration enable signal to generate a ZQ calibration code. The reference code generating circuit may output a predetermined code value as a reference code. The variable information generating circuit may compare the ZQ calibration code to the reference code to generate variable information. The internal circuit may determine operation timings based on a difference between the ZQ calibration code and the reference code.Type: ApplicationFiled: February 22, 2016Publication date: March 2, 2017Inventors: Seung Geun BAEK, Jae Il KIM
-
Publication number: 20170053715Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.Type: ApplicationFiled: November 5, 2015Publication date: February 23, 2017Inventors: Jae Il KIM, Seung Geun BAEK, Don Hyun CHOI
-
Patent number: 9576684Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.Type: GrantFiled: November 5, 2015Date of Patent: February 21, 2017Assignee: SK HYNIX INC.Inventors: Jae Il Kim, Seung Geun Baek, Don Hyun Choi
-
Patent number: 9564194Abstract: An input apparatus of a semiconductor memory may be provided. The input apparatus may include a first storage circuit configured to receive at least a portion of an input signal provided based on a pin reduction command which is enabled before an operation command through a pin and store the at least a portion of the input signal. The input apparatus may include a second storage circuit configured to receive a remaining portion of the input signal provided based on the operation command through the pin and store the remaining portion of the input signal. The input apparatus may include an arrangement circuit configured to control an output timing of the input signal stored in the first storage circuit and the second storage circuit.Type: GrantFiled: April 27, 2016Date of Patent: February 7, 2017Assignee: SK HYNIX INC.Inventors: Seung Geun Baek, Jae Il Kim
-
Publication number: 20160365855Abstract: An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal.Type: ApplicationFiled: October 6, 2015Publication date: December 15, 2016Inventors: Seung Geun BAEK, Jae Il KIM
-
Patent number: 9508410Abstract: A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.Type: GrantFiled: October 28, 2015Date of Patent: November 29, 2016Assignee: SK HYNIX INC.Inventors: Seung Geun Baek, Jae Il Kim
-
Publication number: 20160252572Abstract: A semiconductor integrated circuit device including a variable frequency type probe test pad and a semiconductor system are disclosed. The semiconductor integrated circuit device includes a plurality of probe test pads formed on a semiconductor substrate and configured to induce non-contact electrical coupling with a probe card, and a frequency control unit electrically coupled to each of the plurality of probe test pads, and configured to vary a frequency of each of the plurality of probe test pads.Type: ApplicationFiled: May 28, 2015Publication date: September 1, 2016Inventor: Seung Geun BAEK
-
Patent number: 9374071Abstract: A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.Type: GrantFiled: April 2, 2014Date of Patent: June 21, 2016Assignee: SK hynix Inc.Inventors: Hoon Choi, Seung Geun Baek
-
Patent number: 9203407Abstract: A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.Type: GrantFiled: December 15, 2013Date of Patent: December 1, 2015Assignee: SK Hynix Inc.Inventors: Seung-Geun Baek, Hoon Choi
-
Publication number: 20150226786Abstract: A semiconductor system includes a semiconductor device suitable for generating measuring data, and a controller suitable for comparing the measuring data with a given expected value and controlling a voltage level, which is supplied to the semiconductor device, based on the comparison result.Type: ApplicationFiled: August 6, 2014Publication date: August 13, 2015Inventors: Seung-Geun BAEK, Hoon CHOI
-
Publication number: 20150213845Abstract: A system includes a memory device, a controller, and a power supply. The controller stores a write data in the memory device, and generates a voltage control signal by comparing a read data outputted from the memory device with the write data. The power supply controls a level of a power supply voltage supplied to the memory device in response to the voltage control signal.Type: ApplicationFiled: May 15, 2014Publication date: July 30, 2015Applicant: SK hynix Inc.Inventors: Hoon CHOI, Seung Geun BAEK