Abstract: A nonvolatile memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions include first and second memory regions coupled to upper and lower word lines, respectively. The control logic performs, after receiving first data and second data, a first program operation on the first memory region to store the first data and a second program operation on the second memory region to store the second data.

Abstract: A memory system, a memory controller and an operating method are disclosed. By inputting a read command to the memory device, starting to input data for a write command when the write command is input to the memory device while the memory device performs a read sensing operation for the read command, and inputting, to the memory device, data for the write command when input of the write command is started, it is possible to enhance the write performance of the memory system when the memory system executes a write operation after a read operation.

Abstract: A nonvolatile memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions include first and second memory regions coupled to upper and lower word lines, respectively. The control logic performs, after receiving first data and second data, a first program operation on the first memory region to store the first data and a second program operation on the second memory region to store the second data.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operating method. A command from a host is received and multiple streams corresponding to the command are generated, and the size of super memory blocks is dynamically configured according to the number of multiple streams. Accordingly, the number of currently accessed memory dies can be adjusted according to the number of streams, and the cost for preventing data loss when SPO occurs can be minimized.

Abstract: A memory system, a memory controller and an operating method are disclosed. By inputting a read command to the memory device, starting to input data for a write command when the write command is input to the memory device while the memory device performs a read sensing operation for the read command, and inputting, to the memory device, data for the write command when input of the write command is started, it is possible to enhance the write performance of the memory system when the memory system executes a write operation after a read operation.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operating method. A command from a host is received and multiple streams corresponding to the command are generated, and the size of super memory blocks is dynamically configured according to the number of multiple streams. Accordingly, the number of currently accessed memory dies can be adjusted according to the number of streams, and the cost for preventing data loss when SPO occurs can be minimized.

Abstract: A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.

Abstract: A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.

Abstract: A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.

Abstract: A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.

Abstract: A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.