Abstract: A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.

Abstract: A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.

Abstract: A method and apparatus for bit resolution enhancement and edge enhancement in an electronic device are provided. The method includes determining a Contour Counter (CC) and determining a type of each region of the input image, determining a Bit Resolution Enhancement (BRE) parameter and an edge enhancement parameter of each region according to the determined region type, determining a first weight for each region of the image and enhancing a bit resolution of the input image, and determining a second weight for each region of the image and performing edge enhancement for the image.

Abstract: A method and apparatus for bit resolution enhancement and edge enhancement in an electronic device are provided. The method includes determining a Contour Counter (CC) and determining a type of each region of the input image, determining a Bit Resolution Enhancement (BRE) parameter and an edge enhancement parameter of each region according to the determined region type, determining a first weight for each region of the image and enhancing a bit resolution of the input image, and determining a second weight for each region of the image and performing edge enhancement for the image.

Abstract: An apparatus and method for compensating for data distortion caused by the phase slew of a frame reference signal in a User Equipment (UE) that accesses an asynchronous Wideband Code Division Multiple Access (WCDMA) communication system are provided. In the distortion compensating apparatus, an Finite Impulse Response (FIR) filter receives I channel data and Q channel data, each of the I and Q channel data having a plurality of chips, multiplies the I/Q channel data by a predetermined filtering coefficient, and outputs the product, in synchronization with the frame reference signal. A phase compensator compensates for an I-Q channel exchange occurring at an output end of the FIR filter when the phase of the frame reference signal is advanced or retarded.

Abstract: An apparatus and method for compensating for data distortion caused by the phase slew of a frame reference signal in a User Equipment (UE) that accesses an asynchronous Wideband Code Division Multiple Access (WCDMA) communication system are provided. In the distortion compensating apparatus, an Finite Impulse Response (FIR) filter receives I channel data and Q channel data, each of the I and Q channel data having a plurality of chips, multiplies the I/Q channel data by a predetermined filtering coefficient, and outputs the product, in synchronization with the frame reference signal. A phase compensator compensates for an I-Q channel exchange occurring at an output end of the FIR filter when the phase of the frame reference signal is advanced or retarded.