Abstract: A semiconductor device includes a plurality of logic cells disposed in a first direction, a plurality of filler cells disposed in the first direction, and a power rail configured to apply a voltage to the logic cells and the filler cells, wherein the power rail extending in the first direction and electrically connected to the plurality of logic cells, and a reinforcement pattern disposed in at least one of the plurality of filler cells and electrically connected to the power rail, wherein the reinforcement pattern is electrically connected to the power rail at a plurality of distinct points.

Abstract: A method of manufacturing a semiconductor device includes: forming a plurality of first mandrel patterns at a first mandrel pitch on a substrate; forming a first fin group and a first dummy fin group by patterning the substrate, wherein the first fin group is adjacent to the first dummy fin group in a first direction; and removing the first dummy fin group, wherein the first fin group includes a first fin and a second fin adjacent to each other and arranged at a first fin pitch in the first direction. The first dummy fin group includes a first dummy fin and a second dummy fin adjacent to each other and arranged at the first fin pitch in the first direction. The second fin and the first dummy fin, which is adjacent to the second fin, are arranged at a second fin pitch that is greater than the first fin pitch.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.