Abstract: A wireless communication system, according to one embodiment of the present invention, comprises: a first communication module; and at least one second communication module wirelessly connected to the first communication module, wherein the first communication module is wirelessly connected to the second communication module to which driving power is applied from the same power source as that of the first communication module.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: Memory devices and methods of operating the same are provided. The memory device including at least one internal circuit including a memory cell array and a peripheral circuit configured to drive the memory cell array, a monitor logic configured to monitor a current flowing into the at least one internal circuit and output a monitoring result, a detect logic configured to detect whether a leakage current flows in the at least one internal circuit based on the monitoring result, and output detected information regarding the leakage current, and diagnosis logic configured to diagnose an error in the at least one internal circuit based on the detected information.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).

Abstract: A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: A semiconductor device for controlling a power-up sequence is provided. The semiconductor device includes a plurality of chips. Each of the chips includes a power-up sequence controller configured to differently control generation sequences of internal source voltages. The power-up sequence controller changes the generation sequences of the internal source voltages in response to a power stabilization signal which is generated according to an external source voltage applied thereto in powering up the semiconductor device. Accordingly, a power-up current which is generated according to the internal source voltages being generated has a peak current distribution where a peak current may be equally distributed.

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: A semiconductor device for controlling a power-up sequence is provided. The semiconductor device includes a plurality of chips. Each of the chips includes a power-up sequence controller configured to differently control generation sequences of internal source voltages. The power-up sequence controller changes the generation sequences of the internal source voltages in response to a power stabilization signal which is generated according to an external source voltage applied thereto in powering up the semiconductor device. Accordingly, a power-up current which is generated according to the internal source voltages being generated has a peak current distribution where a peak current may be equally distributed.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.