Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

Abstract: A plasma processing apparatus and a method for fabricating a semiconductor device using the same are provided. The plasma processing apparatus includes: a chuck stage configured to support a wafer thereon; a dielectric ring configured to surround a periphery of the chuck stage, the dielectric ring including a paraelectric material; and a dielectric constant controller configured to control a dielectric constant of the dielectric ring.

Abstract: A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.

Abstract: A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.

Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.