Abstract: The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

Abstract: A semiconductor integrated circuit device and method of forming same is disclosed and includes a silicon substrate having a field oxide region and spaced active region. First and second self-aligned contact window openings are associated with a respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad. A silicon nitride barrier layer is also formed during the process.

Abstract: A contactless, self-aligned local interconnect structure provides a continuous silicide film electrically coupling an upper silicon structure to a lower silicon structure. The upper silicon structure overlaps the lower silicon structure and is insulated from the lower silicon structure by an insulating layer formed between the structures. The continuous silicide film electrically couples the two structures by bridging the gap formed by the insulating layer in the overlap region. The associated process for forming the local interconnect structure includes forming a lateral edge of the upper silicon structure extending over the lower silicon structure, forming a blanket metal film, then heating the metal film such that the metal film reacts with the exposed silicon of the upper silicon structure and the lower silicon structure to form a continuous silicide film which bridges the gap formed by the insulating layer which is formed of a thickness chosen to be suitably low.

Abstract: A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Abstract: An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

Abstract: A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Abstract: To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Abstract: A diffusion barrier for preventing the diffusion of oxygen from a high dielectric constant material to a titanium nitride layer. The diffusion barrier comprises one or more layers, wherein each of the one or more layers comprises a material selected from the group consisting of metal carbide, metal nitride, metal boride, metal carbo-nitride, and silicon carbide. The high dielectric constant material may be tantalum pentoxide or any perkovskite-type high dielectric constant material.

Abstract: A semiconductor integrated circuit device and method of forming same is disclosed and includes a silicon substrate having a field oxide region and spaced active region. First and second self-aligned contact window openings are associated with a respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad. A silicon nitride barrier layer is also formed during the process.

Abstract: An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

Abstract: A method for making a semiconductor device includes forming a plurality of transistors in a semiconductor substrate, forming a first dielectric layer overlying the semiconductor substrate, and selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion. Conducting material is deposited into the first opening to define a merged contact between the first transistor portion and the second transistor portion. The method further includes forming a second dielectric layer overlying the first dielectric layer and the merged contact, and selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor to define a self-aligned contact.

Abstract: The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

Abstract: A method of manufacturing a semiconductor device using shallow trench isolation is provided, wherein a plurality of protrusions are formed in the exposed surface of the mask layer overlying the active area of the device. The protrusions are preferably formed by forming a photo-resist layer on the surface of the mask layer and patterning the photo-resist layer such that the photo-resist layer defines a plurality of protrusion areas and a depression area within the defined active area. A portion of the mask layer is removed in the defined depression area to form a plurality of protrusions in the mask layer. Thereafter, a dielectric layer is deposited on the exposed surface of the mask layer and in the shallow trench and evenly planarized.

Abstract: A capacitor for a DRAM cell comprises a first electrode layer, a second electrode layer, and a dielectric film. The capacitor is disposed in a first opening defined in a second dielectric layer and overlaying a first plug through a first dielectric layer. The first plug is electrically connected to a transistor. The first electrode layer is electrically connected to the first plug. The second electrode layer can act as a barrier between a second plug exposed by a second opening and the second opening. The first and second electrode layer can be formed from Ta and TaN, and the dielectric film can be formed from tantalum oxide. A plug layer electrically connected to the second electrode layer can also be included. The plug layer can be formed from copper. A method of forming the DRAM capacitor is also disclosed.

Abstract: An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.