Patents by Inventor Seung Uk PARK

Seung Uk PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193701
    Abstract: A communication system retrieves profile data corresponding to a user profile of a second user, identifies a status message in the profile data, display, via a user interface of the instant messenger application, the status message; in response to receiving, via the user interface, a user input associated with the status message: query, based on the status message, a database to identify one or more items, and display, via the user interface of the instant messenger application, item data corresponding to the one or more items, receive, via the user interface, a user input associated with the one or more items, instantiate a transaction authentication of the one or more items by causing transmission of transaction information data associated with the first user, and cause, based on the transaction authentication of the one or more items, delivery of the one or more items to an account of the second user.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Inventors: Sul Gi Kim, Ji Hwi Park, Yun Jin Kim, Nam Hee Ko, Hye Seon Kim, Bo Young Jang, Sun Je Bang, Ji On Chu, Seung Yong Ji, Jae Ick Hwang, Eun Ho Son, Sang Min Seo, Jeong Ryeol Choi, Hye Mi Lee, Shin Young Lee, Seung Uk Jeong
  • Publication number: 20240163234
    Abstract: Provided is a method of operating a terminal. The method includes determining a profile item applicable to the profile view for the account based on an input received by the terminal and a coordinate indicating a position where the profile item is provided on the profile view. The method includes displaying the profile item on a screen of the terminal based on the determined profile item and the determined coordinate. The method includes receiving an input related to the profile item, and displaying a visual effect corresponding to the input on the screen.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Sul Gi KIM, Ji Hwi PARK, Yun Jin KIM, Nam Hee KO, Hye Seon KIM, Bo Young JANG, Seung Yong JI, Jae Ick HWANG, Sun Je BANG, Ji On CHU, Hye Mi LEE, Shin Young LEE, Seung Uk JEONG, Eun Ho SON, Sang Min SEO, Jeong Ryeol CHOI
  • Publication number: 20240162478
    Abstract: A lithium secondary battery includes a cathode including a cathode active material that contains lithium metal oxide particles, an anode facing the cathode, and a non-aqueous electrolyte solution including a non-aqueous organic solvent that contains a fluorine-based organic solvent and a lithium salt. A ratio of the number of moles of lithium contained in each of the lithium metal oxide particles to the total number of moles of metals excluding lithium contained in each of the lithium metal oxide particles is 1.05 or more. A content of the fluorine-based organic solvent is in a range from 5 vol % to 60 vol % based on a total volume of the non-aqueous organic solvent.
    Type: Application
    Filed: September 20, 2023
    Publication date: May 16, 2024
    Inventors: Young Uk PARK, In Haeng CHO, Seung Hyun KIM, Ki Sung PARK, Min Woo PARK, Seon Yeong PARK, Yong Hyun CHO
  • Publication number: 20240154112
    Abstract: A cathode active material for a lithium secondary battery according to an embodiment includes lithium metal oxide particles containing lithium and nickel, and containing a small amount of cobalt or no cobalt. An average particle diameter, a modulus and a hardness of the lithium metal oxide particles are adjusted to satisfy a desired relation. A lithium secondary battery has improved high-temperature storage properties, structural stability and high power properties.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Inventors: Hong Ki KIM, Min Gu KANG, Seung Hyun KIM, Young Hoon DO, Young Uk PARK, Yoon Ji LEE, Yong Hyun CHO
  • Patent number: 11923145
    Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked in a first direction and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and external electrodes formed outside the body and connected to the internal electrodes. The body includes an active portion and a side margin portion covering the active portion and opposing each other in a second direction, and 1<A2/M1?1.5 and A2<A1 in which A1 is an average grain size of the dielectric layers in a central region of the active portion, A2 is an average grain size of the dielectric layers at an active boundary part of the active portion adjacent to the side margin portion, and M1 is an average grain size of the dielectric layers in a central region of the side margin portion.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Hee Lee, Seung In Baik, Ji Su Hong, Eun Ha Jang, Hyoung Uk Kim, Jae Sung Park
  • Patent number: 10950845
    Abstract: Provided is a battery protection circuit module package capable of easily achieving high integration and size reduction. The battery protection circuit module package includes a terminal lead frame including a first internal connection terminal lead and a second internal connection terminal lead provided at two edges of the terminal lead frame and electrically connected to electrode terminals of a battery bare cell, and a plurality of external connection terminal leads provided between the first and second internal connection terminal leads and serving as a plurality of external connection terminals, and a device package including a substrate mounted on the terminal lead frame to be electrically connected to the terminal lead frame, and providing a battery protection circuit device thereon.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 16, 2021
    Assignee: ITM SEMICONDUCTOR CO., LTD
    Inventors: Ho-seok Hwang, Young-Seok Kim, Seong-beom Park, Sang-hoon Ahn, Tae Hwan Jung, Seung-uk Park, Jae-ku Park, Myoung-Ki Moon, Hyun-suck Lee, Da-Woon Jung
  • Publication number: 20190157653
    Abstract: Provided is a battery protection circuit module package capable of easily achieving high integration and size reduction. The battery protection circuit module package includes a terminal lead frame including a first internal connection terminal lead and a second internal connection terminal lead provided at two edges of the terminal lead frame and electrically connected to electrode terminals of a battery bare cell, and a plurality of external connection terminal leads provided between the first and second internal connection terminal leads and serving as a plurality of external connection terminals, and a device package including a substrate mounted on the terminal lead frame to be electrically connected to the terminal lead frame, and providing a battery protection circuit device thereon.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Ho-seok HWANG, Young-Seok KIM, Seong-beom PARK, Sang-hoon AHN, Tae Hwan JUNG, Seung-uk PARK, Jae-ku PARK, Myoung-Ki MOON, Hyun-suck LEE, Da-Woon JUNG
  • Patent number: 9787111
    Abstract: Disclosed is a battery protection module package (PMP). The battery PMP according to an embodiment of the present invention includes a lead frame provided with a plurality of external terminals thereon, a printed circuit board stacked on the lead frame, and a plurality of internal terminals, a protection integrated chip (IC), a field effect transistor (FET), resistors, and capacitors disposed on the printed circuit board and electrically connected to each other, wherein the resistors and the capacitors are mounted on a pattern of the printed circuit board using surface mount technology (SMT), and wherein the plurality of internal terminals are electrically connected to the plurality of external terminals.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 10, 2017
    Assignee: ITM SEMICONDUCTOR CO., LTD
    Inventors: Hyeok Hwi Na, Ho Suk Hwang, Young Seok Kim, Sung Beum Park, Sang Hoon Ahn, Tae Hwan Jung, Seung Uk Park, Jae Ku Park, Hyun Mok Cho, Min Ho Park, Young Geun Yoon, Seong Ho Ju, Young Nam Ji, Myoung Ki Moon, Hyun Suck Lee, Ji Young Park
  • Publication number: 20160056444
    Abstract: Disclosed is a battery protection circuit module package capable of easily achieving high integration and size reduction. The battery protection circuit module package includes a terminal lead frame including a first internal connection terminal lead and a second internal connection terminal lead provided at two edges of the terminal lead frame and electrically connected to electrode terminals of a battery bare cell, and a plurality of external connection terminal leads provided between the first and second internal connection terminal leads and serving as a plurality of external connection terminals, and a device package including a substrate mounted on the terminal lead frame to be electrically connected to the terminal lead frame, and providing a battery protection circuit device thereon.
    Type: Application
    Filed: April 17, 2014
    Publication date: February 25, 2016
    Inventors: Ho-seok HWANG, Young-Seok KIM, Seong-beom PARK, Sang-hoon AHN, Tae Hwan JUNG, Seung-uk PARK, Jae-ku PARK, Myoung-Ki MOON, Hyun-suck LEE, Da-Woon JUNG
  • Publication number: 20150333548
    Abstract: Disclosed is a battery protection module package (PMP). The battery PMP according to an embodiment of the present invention includes a lead frame provided with a plurality of external terminals thereon, a printed circuit board stacked on the lead frame, and a plurality of internal terminals, a protection integrated chip (IC), a field effect transistor (FET), resistors, and capacitors disposed on the printed circuit board and electrically connected to each other, wherein the resistors and the capacitors are mounted on a pattern of the printed circuit board using surface mount technology (SMT), and wherein the plurality of internal terminals are electrically connected to the plurality of external terminals.
    Type: Application
    Filed: December 13, 2013
    Publication date: November 19, 2015
    Inventors: Hyeok Hwi NA, Ho Suk HWANG, Young Seok KIM, Sung Beum PARK, Sang Hoon AHN, Tae Hwan JUNG, Seung Uk PARK, Jae Ku PARK, Hyun Mok CHO, Min Ho PARK, Young Geun YOON, Seong Ho JU, Young Nam JI, Myoung Ki MOON, Hyun Suck LEE, Ji Young PARK