Patents by Inventor Seung Wook Yoon
Seung Wook Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12096217Abstract: The present invention relates to a PUF-based IoT device authentication technique, and more specifically, to a PUF-based IoT device using channel state information, and an authentication method thereof. According to an embodiment of the present invention, security of an authentication key may be strengthened by simultaneously utilizing a PUF-based authentication method and an RF characteristic-based authentication method.Type: GrantFiled: June 15, 2022Date of Patent: September 17, 2024Assignee: Gwangju Institute of Science and TechnologyInventors: Eui Seok Hwang, Seung Wook Yoon, Seung Nam Han
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Patent number: 12094729Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: GrantFiled: December 6, 2021Date of Patent: September 17, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Patent number: 11961764Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: GrantFiled: April 15, 2021Date of Patent: April 16, 2024Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Publication number: 20230180002Abstract: The present invention relates to a PUF-based IoT device authentication technique, and more specifically, to a PUF-based IoT device using channel state information, and an authentication method thereof. According to an embodiment of the present invention, security of an authentication key may be strengthened by simultaneously utilizing a PUF-based authentication method and an RF characteristic-based authentication method.Type: ApplicationFiled: June 15, 2022Publication date: June 8, 2023Applicant: Gwangju Institute of Science and TechnologyInventors: Eui Seok HWANG, Seung Wook YOON, Seung Nam HAN
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Publication number: 20220093417Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Patent number: 11257729Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: GrantFiled: September 1, 2019Date of Patent: February 22, 2022Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin
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Patent number: 11222793Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: GrantFiled: November 19, 2019Date of Patent: January 11, 2022Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Publication number: 20210233815Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Applicant: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Patent number: 11011423Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: GrantFiled: November 29, 2018Date of Patent: May 18, 2021Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Patent number: 10903304Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.Type: GrantFiled: March 16, 2017Date of Patent: January 26, 2021Assignee: STATS ChipPAC Pte. Ltd.Inventors: Meenakshi Padmanathan, Seung Wook Yoon, YongTaek Lee
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Patent number: 10622293Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.Type: GrantFiled: January 27, 2016Date of Patent: April 14, 2020Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
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Publication number: 20200090954Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: ApplicationFiled: November 19, 2019Publication date: March 19, 2020Applicant: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Publication number: 20200006177Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: ApplicationFiled: September 1, 2019Publication date: January 2, 2020Applicant: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin
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Method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
Patent number: 10515828Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: GrantFiled: September 23, 2016Date of Patent: December 24, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu -
Patent number: 10475779Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.Type: GrantFiled: August 14, 2017Date of Patent: November 12, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Yaojian Lin, Kang Chen, Seung Wook Yoon
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Patent number: 10446459Abstract: A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.Type: GrantFiled: June 9, 2017Date of Patent: October 15, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Seung Wook Yoon, Yaojian Lin
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Publication number: 20190109048Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: ApplicationFiled: November 29, 2018Publication date: April 11, 2019Applicant: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Patent number: 10213396Abstract: There is provided a patch to enhance locally fat metabolism, using a thermoplastic elastomer gel composition including capsaicin, which is applied to the skin surface, comprises: a skin adhering layer formed of the thermoplastic elastomer (TPE) gel including capsaicin, the skin adhering layer having a top surface and a bottom surface; a base layer secured to the bottom surface of the skin adhering layer, to support for the patch; and a removable paper/film layer secured to the top surface of the skin adhering layer, to protect the skin adhering layer prior to use, wherein the skin adhering layer comprises: 3˜12 wt % of styrene ethylene butylene styrene (SEBS) or styrene ethylene ethylene propylene styrene (SEEPS), 44˜53 wt % of an adhesive agent; 44˜53 wt % of mineral oil, and 0.001˜0.009 wt % of capsaicin. Capsaicin included in the TPE gel derives heat generation and fat breakdown, to help attain fat loss in the area where the patch is applied.Type: GrantFiled: July 13, 2017Date of Patent: February 26, 2019Assignee: SENNY STUDIO CO., LTD.Inventors: Kyu-Hak Cho, Seung-Wook Yoon
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Publication number: 20190015359Abstract: There is provided a patch to enhance locally fat metabolism, using a thermoplastic elastomer gel composition including capsaicin, which is applied to the skin surface, comprises: a skin adhering layer formed of the thermoplastic elastomer (TPE) gel including capsaicin, the skin adhering layer having a top surface and a bottom surface; a base layer secured to the bottom surface of the skin adhering layer, to support for the patch; and a removable paper/film layer secured to the top surface of the skin adhering layer, to protect the skin adhering layer prior to use, wherein the skin adhering layer comprises: 3˜12 wt % of styrene ethylene butylene styrene (SEBS) or styrene ethylene ethylene propylene styrene (SEEPS), 44˜53 wt % of an adhesive agent; 44˜53 wt % of mineral oil, and 0.001˜0.009 wt % of capsaicin. Capsaicin included in the TPE gel derives heat generation and fat breakdown, to help attain fat loss in the area where the patch is applied.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventors: Kyu-Hak CHO, Seung-Wook YOON
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Patent number: 10181423Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: GrantFiled: January 24, 2017Date of Patent: January 15, 2019Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu