Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Abstract: A memory device is provided. The memory device includes: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip which overlaps the first chip along a vertical direction. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low-voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low-voltage transistor.

Abstract: A platform system includes a station including a moving portion and a guide configured to guide movement of the moving portion, and a manipulator configured to pick up an object from the moving portion or to place the object on the moving portion, where the moving portion is configured to move in response to the manipulator picking up the object from the moving portion or placing the object on the moving portion.

Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

Abstract: A three-dimensional (3D) semiconductor memory device is provided. The device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including memory cells arranged vertically along a vertical direction; and a connection region including ends of word lines that are connected to the memory cells, wherein the ends form a stair-step configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region along the vertical direction. The peripheral circuit region includes a first main pass transistor electrically connected to a first word line of the word lines, and a first dummy pass transistor electrically separated from the word lines. The first main pass transistor and the first dummy pass transistor are arranged along a first direction perpendicular to the vertical direction.

Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

Abstract: Implementations disclose selecting, in response to receiving a request and from among multiple candidate generative models (e.g., multiple candidate large language models (LLMs)) with differing computational efficiencies, a particular generative model to utilize in generating a response to the request. Those implementations reduce latency and/or conserve computational resource(s) through selection, for various requests, of a more computationally efficient generative model for utilization in lieu of a less computationally efficient generative model. Further, those implementations seek to achieve such benefits, through utilization of more computationally efficient generative models, while also still selectively utilizing less computationally efficient generative models for certain requests to mitigate occurrences of a generated response being inaccurate and/or under-specified.

Abstract: The present invention relates to a novel MKRN1 inhibitor and a medicinal use thereof. Specifically, the present invention relates to a method of treating obesity, diabetes, fatty liver disease, and/or steatohepatitis by administering ebastine to a subject in need of treatment.

Abstract: Generally, the present disclosure is directed to systems and methods that perform adaptive optimization with improved convergence properties. The adaptive optimization techniques described herein are useful in various optimization scenarios, including, for example, training a machine-learned model such as, for example, a neural network. In particular, according to one aspect of the present disclosure, a system implementing the adaptive optimization technique can, over a plurality of iterations, employ an adaptive per coordinate clipping threshold to clip a current first moment of the coordinate to obtain a current update value that enables faster convergence for the machine-learned model when the noise in the stochastic gradients is heavy tailed.

Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Abstract: A semiconductor memory includes a substrate that includes pass transistor regions, a peripheral circuit structure that includes pass transistors on the pass transistor regions, and a cell array structure on the peripheral circuit structure, the cell array structure including a plurality of cell array regions and a plurality of connection regions that are alternately arranged along a first direction. The cell array structure includes a stack structure including conductive patterns vertically stacked and correspondingly connected to the pass transistors. The stack structure includes stepwise structures on the connection regions. The connection regions of the cell array structure correspondingly overlap the pass transistor regions of the peripheral circuit structure.

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Abstract: A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.

Abstract: A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area.

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction and word lines each extending in a second direction and stacked in a vertical direction, word line pads which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width in the first direction and a second width in the second direction. Each of the pass transistors has a first pitch in the first direction and a second pitch in the second direction.

Abstract: A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

Abstract: A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

Abstract: The present disclosure is directed to input suggestion. In particular, the methods and systems of the present disclosure can: receive, from a first application executed by one or more computing devices, data indicating information that has been presented by and/or input into the first application; generate, based at least in part on the received data, one or more suggested candidate inputs for a second application executed by the computing device(s); provide, in association with the second application, an interface comprising one or more options to select at least one suggested candidate input of the suggested candidate input(s); and responsive to receiving data indicating a selection of a particular suggested candidate input of the suggested candidate input(s) via the interface, communicate, to the second application, data indicating the particular suggested candidate input.

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Abstract: The present disclosure is directed to input suggestion. In particular, the methods and systems of the present disclosure can: receive, from a first application executed by one or more computing devices, data indicating information that has been presented by and/or input into the first application; generate, based at least in part on the received data, one or more suggested candidate inputs for a second application executed by the computing device(s); provide, in association with the second application, an interface comprising one or more options to select at least one suggested candidate input of the suggested candidate input(s); and responsive to receiving data indicating a selection of a particular suggested candidate input of the suggested candidate input(s) via the interface, communicate, to the second application, data indicating the particular suggested candidate input.