Abstract: A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers.

Abstract: A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.