Patents by Inventor Seungyoon JUNG

Seungyoon JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240160115
    Abstract: Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.
    Type: Application
    Filed: July 5, 2023
    Publication date: May 16, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Wooyong JUNG, Dohun KIM, Joonhyun KIM, Jeongjin LEE, Seungyoon LEE, Chan HWANG
  • Publication number: 20240162193
    Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. The lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. The upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.
    Type: Application
    Filed: June 25, 2023
    Publication date: May 16, 2024
    Inventors: Seongyo KIM, UN-BYOUNG KANG, SANG-SICK PARK, Hanmin LEE, Seungyoon JUNG
  • Publication number: 20230230946
    Abstract: A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.
    Type: Application
    Filed: September 7, 2022
    Publication date: July 20, 2023
    Inventors: Seongyo KIM, UN-BYOUNG KANG, MINSOO KIM, SANG-SICK PARK, Seungyoon JUNG