Patents by Inventor SeungYun Ahn

SeungYun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330945
    Abstract: An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae, Jong-Woo Ha
  • Patent number: 9093391
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 28, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: SeungYun Ahn, JoHyun Bae, SangJin Lee
  • Patent number: 8643181
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: February 4, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, SeongHun Mun, SeungYun Ahn
  • Patent number: 8609463
    Abstract: An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: December 17, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, SeungYun Ahn, DongSoo Moon
  • Patent number: 8535981
    Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a bottom package in a cavity in a central region of the bottom package having inter-package interconnects in the cavity; forming a vent on an inter-package connection side of the bottom package from an exterior of the bottom package to the cavity; mounting a top package on the inter-package interconnects; and applying an underfill through the vent and into the cavity.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 17, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Chan Hoon Ko, SeungYun Ahn
  • Patent number: 8501535
    Abstract: A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Publication number: 20120228753
    Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a bottom package in a cavity in a central region of the bottom package having inter-package interconnects in the cavity; forming a vent on an inter-package connection side of the bottom package from an exterior of the bottom package to the cavity; mounting a top package on the inter-package interconnects; and applying an underfill through the vent and into the cavity.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 13, 2012
    Inventors: Chan Hoon Ko, SeungYun Ahn
  • Patent number: 8258008
    Abstract: A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: September 4, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee, SeungYun Ahn
  • Patent number: 8221583
    Abstract: A semiconductor system for peeling semiconductor chips from tape, comprising: providing an outer housing having an aperture on a top thereof; providing a magnet with a needle base extension; providing needles magnetically held to the magnet; applying a vacuum through the aperture to hold an adhesive material to the outer housing; and extending the needles through the aperture in the outer housing.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: July 17, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Gab Yong Min, Dong Hyong Lee, Jung Ho Kim, SeungYun Ahn
  • Patent number: 8067306
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, SeungYun Ahn
  • Publication number: 20110233751
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 29, 2011
    Inventors: JoHyun Bae, SeongHun Mun, SeungYun Ahn
  • Publication number: 20110210437
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Inventors: DeokKyung Yang, SeungYun Ahn
  • Publication number: 20110115098
    Abstract: A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 19, 2011
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Publication number: 20110084401
    Abstract: A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 14, 2011
    Inventors: Taewoo Lee, Sang-Ho Lee, SeungYun Ahn
  • Publication number: 20110062602
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Inventors: SeungYun Ahn, JoHyun Bae, SangJin Lee
  • Patent number: 7884457
    Abstract: An integrated circuit package system comprising: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 8, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Patent number: 7863755
    Abstract: A package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee, SeungYun Ahn
  • Publication number: 20090236752
    Abstract: A package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Inventors: Taewoo Lee, Sang-Ho Lee, SeungYun Ahn
  • Patent number: 7521297
    Abstract: A multichip package system is provided forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: April 21, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: SeongMin Lee, SeungYun Ahn, Koo Hong Lee
  • Publication number: 20090072375
    Abstract: An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae, Jong-Woo Ha