Patents by Inventor Severine Cheramy

Severine Cheramy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11694991
    Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: July 4, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank Fournel, Emilie Bourjot, Séverine Cheramy, Sylvain Maitrejean, Loic Sanchez
  • Patent number: 11482567
    Abstract: A display device including a first integrated circuit including: an assembly of light-emitting diodes, each diode including a vertical stack of a first semiconductor layer of a first conductivity type and of a second semiconductor layer of a second conductivity type; and on the side of a surface of the first circuit opposite to the first semiconductor layer, a connection structure including a dielectric layer having a plurality of identical or similar connection pads, regularly distributed across the entire surface of the first circuit, arranged therein, each diode having a first electrode in contact with at least one pad of the connection structure, and a second electrode in contact with a plurality of pads of the connection structure at the periphery of the plurality of diodes.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 25, 2022
    Assignee: Commissariat á l'Énergie Atomique et aux Énergies Alternatives
    Inventors: François Templier, Séverine Cheramy, Frank Fournel
  • Publication number: 20210407961
    Abstract: A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank FOURNEL, Emilie BOURJOT, Séverine CHERAMY, Sylvain MAITREJEAN, Loic SANCHEZ
  • Patent number: 11114818
    Abstract: A photonic chip includes an optical layer bonded, at a bonding interface, to an interconnection layer, the thickness of the optical layer being smaller than 15 ?m, a primary via that extends through the interconnection layer solely between a lower face and the bonding interface, an electrical terminal chosen from the group consisting of an electrical contact embedded in the interior of the optical layer and of an electrical track produced on an upper face, a second via that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer from the bonding interface to the electrical terminal, the maximum diameter of this secondary via being smaller than 3 ?m.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 7, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Sylvie Menezo, Severine Cheramy
  • Publication number: 20210234334
    Abstract: A photonic chip includes an optical layer bonded, via a bonding interface, to a carrier, and a laser source having a waveguide encapsulated in an encapsulating sublayer of the optical layer, the waveguide having a first electrical contact embedded in the encapsulating sublayer. The photonic chip also includes an interconnect metal network forming a via that extends, in the optical layer, from the bonding interface to the first embedded electrical contact of the waveguide, the interconnect metal network having metal vias that electrically connect to one another metals lines that extend mainly parallel to the plane of the chip, the metal lines being arranged one above the other within the optical layer.
    Type: Application
    Filed: May 14, 2019
    Publication date: July 29, 2021
    Applicant: COMMISSARIAT A L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Sylvie MENEZO, Séverine CHERAMY
  • Publication number: 20210020688
    Abstract: A display device including a first integrated circuit including: an assembly of light-emitting diodes, each diode including a vertical stack of a first semiconductor layer of a first conductivity type and of a second semiconductor layer of a second conductivity type; and on the side of a surface of the first circuit opposite to the first semiconductor layer, a connection structure including a dielectric layer having a plurality of identical or similar connection pads, regularly distributed across the entire surface of the first circuit, arranged therein, each diode having a first electrode in contact with at least one pad of the connection structure, and a second electrode in contact with a plurality of pads of the connection structure at the periphery of the plurality of diodes.
    Type: Application
    Filed: March 18, 2019
    Publication date: January 21, 2021
    Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives
    Inventors: François Templier, Séverine Cheramy, Frank Fournel
  • Publication number: 20190379177
    Abstract: A photonic chip includes an optical layer bonded, at a bonding interface, to an interconnection layer, the thickness of the optical layer being smaller than 15 ?m, a primary via that extends through the interconnection layer solely between a lower face and the bonding interface, an electrical terminal chosen from the group consisting of an electrical contact embedded in the interior of the optical layer and of an electrical track produced on an upper face, a second via that extends the primary via into the interior of the optical layer in order to electrically connect the primary via to the electrical terminal, this secondary via extending in the interior of the optical layer from the bonding interface to the electrical terminal, the maximum diameter of this secondary via being smaller than 3 ?m.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 12, 2019
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Sylvie MENEZO, Severine Cheramy
  • Patent number: 10438921
    Abstract: A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 8, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank Fournel, Xavier Baillin, Séverine Cheramy, Patrick Leduc, Loic Sanchez
  • Publication number: 20180301433
    Abstract: A method of manufacturing an emissive LED display device, including the steps of forming a plurality of chips, each including at least one LED and, on a connection surface, a plurality of hydrophilic electric connection areas and a hydrophobic area; forming a transfer substrate including, for each chip, a plurality of hydrophilic electric connection areas and a hydrophobic area; arranging a drop of a liquid on each electric connection area of the transfer substrate and/or of each chip; and affixing the chips to the transfer substrate by direct bonding, using the capillary restoring force of the drops to align the electric connection areas of the chips with the electric connection areas of the transfer substrate.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 18, 2018
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Ivan-Christophe Robin, Jean Berthier, Séverine Cheramy, Léa Di Cioccio
  • Publication number: 20180218997
    Abstract: A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip.
    Type: Application
    Filed: July 26, 2016
    Publication date: August 2, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank FOURNEL, Xavier BAILLIN, Séverine CHERAMY, Patrick LEDUC, Loic SANCHEZ
  • Patent number: 9543287
    Abstract: This integrated circuit comprises: a substrate, a first electrical conductor comprising a first end, the first electrical conductor being electrically insulated from the substrate, a second electrical conductor comprising a second end, the second electrical conductor being electrically insulated from the substrate and electrically insulated from the first electrical conductor except at the second end which is mechanically and electrically directly in contact with the first end to form an electrical junction. The first and second ends are entirely buried to at least 5 ?m depth inside the substrate and produced, respectively, in different first and second materials chosen for the absolute value of the Seebeck coefficient of the junction to be greater than 1 ?V/K at 20° C. such that the combination of these first and second conductors forms a temperature probe.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 10, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Severine Cheramy
  • Patent number: 8973834
    Abstract: A secured identification document has at least two flexible layers embedding an electronic module. The electronic module includes a flexible substrate on which are positioned an antenna and a radiofrequency microcontroller storing identification data. The radiofrequency microcontroller is electrically connected to said antenna. The secured identification document has the at least two flexible layers locally joined together by means of a chemically and mechanically tamper proof material that is applied in cavities that are distributed in each of said at least two flexible layers that surround the electronic module in order to make the electronic module interdependent with the at least two flexible layers.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: March 10, 2015
    Assignee: Gemalto SA
    Inventors: Yves Reignoux, Joseph Jerome Leibenguth, Severine Cheramy, Denis Groeninck, Denis Vere, Francois Roussel
  • Publication number: 20140183533
    Abstract: This integrated circuit comprises: a substrate, a first electrical conductor comprising a first end, the first electrical conductor being electrically insulated from the substrate, a second electrical conductor comprising a second end, the second electrical conductor being electrically insulated from the substrate and electrically insulated from the first electrical conductor except at the second end which is mechanically and electrically directly in contact with the first end to form an electrical junction. The first and second ends are entirely buried to at least 5 ?m depth inside the substrate and produced, respectively, in different first and second materials chosen for the absolute value of the Seebeck coefficient of the junction to be greater than 1 ?V/K at 20° C. such that the combination of these first and second conductors forms a temperature probe.
    Type: Application
    Filed: December 20, 2013
    Publication date: July 3, 2014
    Inventor: Severine Cheramy
  • Patent number: 8487828
    Abstract: A document with a cover having a first cover part, a second cover part, at least one internal page located between the two cover parts when the document is closed, a radiofrequency microcontroller, an antenna electrically connected to the radiofrequency microcontroller, and an electromagnetic shield capable of disrupting, at least partially, the wireless communication with the radiofrequency microcontroller when the document is closed and not disrupting the wireless communication when the document is opened. The electromagnetic shield is a wire grid. The wire mesh distance between each two adjacent wires of the wire grid is smaller than a radio-frequency wavelength used for communicating with the radiofrequency microcontroller, and is at least 0.1 millimeters and at most 40 millimeters.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 16, 2013
    Assignee: Gemalto, SA
    Inventors: Bart Bombay, Neville Pattinson, Ksheerabdhi Krishna, Jean-Pierre Lafon, Joseph Leibenguth, Denis Groeninck, Yves Reignoux, Severine Cheramy
  • Publication number: 20110114732
    Abstract: A secured identification document has at least two flexible layers embedding an electronic module. The electronic module includes a flexible substrate on which are positioned an antenna and a radiofrequency microcontroller storing identification data. The radiofrequency microcontroller is electrically connected to said antenna. The secured identification document has the at least two flexible layers locally joined together by means of a chemically and mechanically tamper proof material that is applied in cavities that are distributed in each of said at least two flexible layers that surround the electronic module in order to make the electronic module interdependent with the at least two flexible layers.
    Type: Application
    Filed: April 18, 2005
    Publication date: May 19, 2011
    Applicant: AXALTO SA
    Inventors: Yves Reignoux, Joseph Jerome Leibenguth, Severine Cheramy, Denis Groeninck, Denis Vere, Francois Roussel
  • Publication number: 20100141547
    Abstract: A document with a cover having a first cover part, a second cover part, at least one internal page located between the two cover parts when the document is closed, a radiofrequency microcontroller, an antenna electrically connected to the radiofrequency microcontroller, and an electromagnetic shield capable of disrupting, at least partially, the wireless communication with the radiofrequency microcontroller when the document is closed and not disrupting the wireless communication when the document is opened. The electromagnetic shield is a wire grid. The wire mesh distance between each two adjacent wires of the wire grid is smaller than a radio-frequency wavelength used for communicating with the radiofrequency microcontroller, and is at least 0.1 millimeters and at most 40 millimeters.
    Type: Application
    Filed: February 10, 2010
    Publication date: June 10, 2010
    Applicant: AXALTO SA
    Inventors: Bart Bombay, Neville Pattinson, Ksheerabdhi Krishna, Jean-Pierre Lafon, Joseph Leibenguth, Denis Groeninck, Yves Reignoux, Severine Cheramy
  • Patent number: 7701408
    Abstract: A document which includes a cover, one or more internal pages, a radiofrequency microcontroller, an antenna electrically connected to the radiofrequency microcontroller, an electromagnetic shield capable of partially disrupting wireless communication with the radiofrequency microcontroller when the document is closed, and not disrupting the wireless communication when the document is opened is described. The electromagnetic shield included in the document is implemented using metal, conductive plastic, conductive ink or magnetic ink.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: April 20, 2010
    Assignee: Axalto SA
    Inventors: Bart Bombay, Neville Pattinson, Ksheerabdhi Krishna, Yves Reignoux, Severine Cheramy, Joseph Leibenguth, Denis Groeninck, Jean-Pierre Lafon
  • Publication number: 20070205953
    Abstract: A document which includes a cover, one or more internal pages, a radiofrequency microcontroller, an antenna electrically connected to the radiofrequency microcontroller, an electromagnetic shield capable of partially disrupting wireless communication with the radiofrequency microcontroller when the document is closed, and not disrupting the wireless communication when the document is opened is described. The electromagnetic shield included in the document is implemented using metal, conductive plastic, conductive ink or magnetic ink.
    Type: Application
    Filed: April 1, 2005
    Publication date: September 6, 2007
    Applicant: AXALTO SA
    Inventors: Bart Bombay, Neville Pattinson, Ksheerabdhi Krishna, Yves Reignoux, Severine Cheramy, Joseph Leibenguth, Denis Groeninck, Jean-Pierre Lafon