Patents by Inventor Severino A. Legaspi
Severino A. Legaspi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140260650Abstract: Circuits, methods, and apparatus that provide pressure sensor devices where pressure sensors may be reliably attached to surfaces in device packages, and where the coefficients of expansion of the pressure sensor and the surface are at least approximately equal. Examples may provide pressure sensor devices where pressure sensors may be reliably attached to surfaces in device packages by providing interposers formed to prevent adhesives used to attach the pressure sensors to surfaces from blocking or encroaching into pressure sensor openings or cavities. These same features may be used to accurately locate a pressure sensor relative to the interposer. Embodiments of the present invention may provide pressure sensor devices where the coefficients of expansion of the pressure sensor and the surface are at least approximately equal by proving interposers that are formed of the same or similar material as the pressure sensors, such as silicon.Type: ApplicationFiled: September 10, 2013Publication date: September 18, 2014Applicant: Silicon Microstructures, Inc.Inventors: Holger Doering, Richard J. August, Severino Legaspi
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Patent number: 7436060Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.Type: GrantFiled: June 9, 2004Date of Patent: October 14, 2008Assignee: LSI CorporationInventors: Pradip Patel, Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr.
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Publication number: 20050275086Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.Type: ApplicationFiled: June 9, 2004Publication date: December 15, 2005Inventors: Pradip Patel, Maurice Othieno, Manickam Thavarajah, Severino Legaspi
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Patent number: 6933602Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls.Type: GrantFiled: July 14, 2003Date of Patent: August 23, 2005Assignee: LSI Logic CorporationInventors: Pradip Patel, Maurice Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr.
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Patent number: 6867480Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.Type: GrantFiled: June 10, 2003Date of Patent: March 15, 2005Assignee: LSI Logic CorporationInventors: Severino A. Legaspi, Jr., Manickam Thavarajah, Maurice O. Othieno, Pradip D. Patel
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Publication number: 20040251522Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.Type: ApplicationFiled: June 10, 2003Publication date: December 16, 2004Inventors: Severino A. Legaspi, Manickam Thavarajah, Maurice O. Othieno, Pradip D. Patel
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Patent number: 6801437Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.Type: GrantFiled: January 21, 2003Date of Patent: October 5, 2004Assignee: LSI Logic CorporationInventors: Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr., Pradip D. Patel
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Patent number: 6777803Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.Type: GrantFiled: August 28, 2002Date of Patent: August 17, 2004Assignee: LSI Logic CorporationInventors: Maurice Othieno, Aritharan Thurairajaratnam, Manickam Thavarajah, Pradip D. Patei, Severino A. Legaspi, Jr.
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Publication number: 20040142556Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.Type: ApplicationFiled: January 21, 2003Publication date: July 22, 2004Inventors: Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Pradip D. Patel
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Publication number: 20040041252Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.Type: ApplicationFiled: August 28, 2002Publication date: March 4, 2004Inventors: Maurice Othieno, Aritharan Thurairajaratnam, Manickam Thavarajah, Pradip D. Patel, Severino A. Legaspi
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Patent number: 6603201Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.Type: GrantFiled: October 23, 2002Date of Patent: August 5, 2003Assignee: LSI Logic CorporationInventors: Manickam Thavarajah, Maurice O. Othieno, Severino A. Legaspi, Jr., Pradip D. Patel