Patents by Inventor Sevgui Hadjihassan

Sevgui Hadjihassan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash ADC receiver with reduced errors
    Patent number: 6980140
    Abstract: Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: December 27, 2005
    Assignee: Nortel Networks Limited
    Inventors: Andy Rowland, Tom Luk, Sevgui Hadjihassan
  • FLASH ADC RECEIVER WITH REDUCED ERRORS
    Publication number: 20050280568
    Abstract: Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.
    Type: Application
    Filed: June 18, 2004
    Publication date: December 22, 2005
    Inventors: Andy Rowland, Tom Luk, Sevgui Hadjihassan
  • Method and apparatus for adjusting receiver voltage threshold and phase sampling point using FEC counts
    Patent number: 6871304
    Abstract: Methods and apparatus are provided for adjusting slicing parameters, such as a voltage threshold and a phase sampling point, used in recovering 1's and 0's from a signal so as to reduce a bit error rate (BER) of the signal. The BER is modelled as a second order polynomial of the slicing parameters. The BER is repeatedly determined from a Forward Error Correction corrected bits counter. For each BER measurement the model is updated, using for example a recursive least squares fit. New values of the slicing parameters are then determined by carrying out an iteration of an optimization, such as a Levenberg-Marquardt optimization, using the model. The new values of the slicing parameters are passed to a Clock and Data Recovery module. Various conditions are checked before updating the model or determining the new values of the slicing parameters, such as changes in signal power or high BERs which exceed the error correction capabilities of the forward error correction.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: March 22, 2005
    Assignee: Nortel Networks Limited
    Inventors: Sevgui Hadjihassan, Tom M. Luk
  • Method and apparatus for adjusting receiver voltage threshold and phase sampling point using FEC counts
    Publication number: 20040030965
    Abstract: Methods and apparatus are provided for adjusting slicing parameters, such as a voltage threshold and a phase sampling point, used in recovering 1's and 0's from a signal so as to reduce a bit error rate (BER) of the signal. The BER is modelled as a second order polynomial of the slicing parameters. The BER is repeatedly determined from a Forward Error Correction corrected bits counter. For each BER measurement the model is updated, using for example a recursive least squares fit. New values of the slicing parameters are then determined by carrying out an iteration of an optimization, such as a Levenberg-Marquardt optimization, using the model. The new values of the slicing parameters are passed to a Clock and Data Recovery module. Various conditions are checked before updating the model or determining the new values of the slicing parameters, such as changes in signal power or high BERs which exceed the error correction capabilities of the forward error correction.
    Type: Application
    Filed: August 12, 2002
    Publication date: February 12, 2004
    Inventors: Sevgui Hadjihassan, Tom M. Luk