Abstract: A vector cumulative sum circuit can include a set of input registers, a carry-forward data source, a set of output registers, and a network of adder circuits coupling the input registers to the output registers such that the output value in a given output register is the sum of a value provided by the carry-forward data source and the input values from all of the input registers (in logical order) up to (and including) the corresponding input register. The value in the last output register can be carried forward to enable cumulative summing of a larger number of input values. The vector cumulative sum circuit can be implemented in a programmable processor, and a vector cumulative sum instruction can be defined in the instruction set. Using the vector cumulative sum circuit and instruction, filtering operations can be accelerated.

Abstract: Vector sort circuits that can be used to accelerate sorting operations in a vector processor. When a new data element is received, the vector sort circuit can read multiple existing data elements from a vector-sort database in parallel, compare metrics of the existing data elements to a metric of the new data element, and output updated data elements to the vector-sort database based on the metrics. Depending on implementation, the vector-sort database can be maintained in sorted order, or the data elements can have assigned ranks indicating the sort order and the elements need not be stored in sorted order. A vector sort circuit can be incorporated into a vector sort functional unit of a microprocessor, and the instruction set of the microprocessor can include instructions that are executed by the vector sort functional unit using the vector sort circuit.

Abstract: A Cartesian transmitter and a method of linearizing a Cartesian transmitter. In one embodiment, the transmitter includes: (1) a transmit chain configured to receive an input signal having in-phase and quadrature components and having a predistorter configured to employ at least one compensation lookup table to carry out in-phase and quadrature compensation predistortion with respect to the input signal, a combiner configured to combine outputs of the predistorter and a nonlinear element configured to process an output of the combiner, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update the at least one compensation lookup table based on the input signal and a signal from the receiver.

Abstract: A polar transmitter and a method of linearizing a polar transmitter. In one embodiment, the transmitter includes: (1) a transmit chain having a predistorter configured to employ first amplitude and phase compensation lookup tables to carry out predistortion in the transmit chain, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update second amplitude and phase compensation lookup tables associated therewith based on at least one signal from the transmit chain, the values in the updated second amplitude and phase compensation lookup tables thereby available for subsequent predistortion.

Abstract: A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the lookup table and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the lookup table.

Abstract: A Cartesian transmitter and a method of linearizing a Cartesian transmitter. In one embodiment, the transmitter includes: (1) a transmit chain configured to receive an input signal having in-phase and quadrature components and having a predistorter configured to employ at least one compensation lookup table to carry out in-phase and quadrature compensation predistortion with respect to the input signal, a combiner configured to combine outputs of the predistorter and a nonlinear element configured to process an output of the combiner, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update the at least one compensation lookup table based on the input signal and a signal from the receiver.

Abstract: A polar transmitter and a method of linearizing a polar transmitter. In one embodiment, the transmitter includes: (1) a transmit chain having a predistorter configured to employ first amplitude and phase compensation lookup tables to carry out predistortion in the transmit chain, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update second amplitude and phase compensation lookup tables associated therewith based on at least one signal from the transmit chain, the values in the updated second amplitude and phase compensation lookup tables thereby available for subsequent predistortion.

Abstract: A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the lookup table and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the lookup table.