Patents by Inventor Seyed ATTARAN

Seyed ATTARAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits
    Patent number: 9209137
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: December 8, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Duc Anh Vu, Jayalakshmana Kumar Pragasam, Vijay Meduri, Seyed Attaran, Michael J. Grubisich, Syed Ahmed, Aniket Singh
  • MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS
    Publication number: 20140327115
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Duc Anh VU, Jayalakshmana Kumar PRAGASAM, Vijay MEDURI, Seyed ATTARAN, Michael J. GRUBISICH, Syed AHMED, Aniket SINGH
  • Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits
    Patent number: 8785246
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 22, 2014
    Assignee: PLX Technology, Inc.
    Inventors: Duc Anh Vu, Jayalakshmana Kumar Pragasam, Vijay Meduri, Seyed Attaran, Michael J. Grubisich, Syed Ahmed, Aniket Singh
  • MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS
    Publication number: 20140035106
    Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: PLX TECHNOLOGY, INC.
    Inventors: Duc Anh VU, Jayalakshmana Kumar PRAGASAM, Vijay MEDURI, Seyed ATTARAN, Michael J. GRUBISICH, Syed AHMED, Aniket SINGH