Patents by Inventor Seyed Morteza Alavi

Seyed Morteza Alavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146346
    Abstract: A method of applying an activation scheme to a digitally controlled segmented RF power transmitter having a plurality of adjacent segments (3), each segment (3) having an associated activation area, the segments (3) being controlled by one or more code words (CWD) The method includes controlling segments (3) by activating a specific segment (3) using an activation scheme for activating specific ones of the segments (3) depending on the code word (CWD), the activation scheme starting from center ones of the plurality of segments (3) towards outer ones of the plurality of segments (3) for increasing code word (CWD) values. This method can be applied in any digitally controlled segmented RF power transmitter, be it in polar or Cartesian implementations, and in single ended or push-pull output configurations.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 2, 2024
    Applicant: TECHNISCHE UNIVERSITEIT DELFT
    Inventors: Dieuwert Peter Nicolaas Mul, Robert Jan Bootsman, Mohammad Reza Beikmirza, Seyed Morteza Alavi, Leonardus Cornelis Nicolaas de Vreede
  • Publication number: 20240146503
    Abstract: Digitally controlled segmented RF power transmitter with a digital processing part (2) and an RF power amplification part (3) having a plurality of segments (122). The digital processing part (2) has a clock generation block (5) being arranged to generate n equi-phased clock signals with a 50% duty-cycle (fLO,x_50%; Cx), and a sign-bit phase mapper unit (11) being arranged to receive the n equi-phased clock signals (fLO,x_50%; Cx), and sign signals (SignI, SignQ; sign bits), and to output a set of m, m?n, phase mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy) using a predetermined phase swapping scheme. Each of the plurality of segments (122) comprises logic circuitry (12) receiving the set of m phase-mapped clock signals with a 50% duty-cycle (CLKy,50%; Cy), and being arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 2, 2024
    Applicant: Technische Universiteit Delft
    Inventors: Mohammad Reza Beikmirza, Leonardus Cornelis Nicolaas de Vreede, Robert Jan Bootsman, Dieuwert Peter Nicolaas Mul, Seyed Morteza Alavi, Yiyu Shen
  • Publication number: 20240106396
    Abstract: The present invention relates to a push-pull amplifying unit and a Doherty amplifier. The push-pull amplifying unit comprises a first amplifier, a second amplifier, a first shunt inductor, and a second shunt inductor. The first and second shunt inductors have mutually connected second terminals and are inductively coupled to increase the impedance between the first output and the virtual ground and the impedance between the second output and the virtual ground at a fundamental frequency of a signal to be amplified by the push-pull amplifying unit relative to those impedances in the absence of said inductive coupling, and to decrease the impedance between the first output and the virtual ground and the impedance between the second output and the virtual ground at a second harmonic frequency of the signal to be amplified relative to those impedances in the absence of said inductive coupling.
    Type: Application
    Filed: February 4, 2022
    Publication date: March 28, 2024
    Inventors: Mohammad Reza BEIKMIRZA, Seyed Morteza ALAVI, Leonardus Cornelis Nicolaas DE VREEDE, Freerk VAN RIJS, Radjindrepersad GAJADHARSING
  • Publication number: 20230143414
    Abstract: An RF transmitter having one or more common-gate, CG, or common-base, CB, configured output stages, and a digitally controlled current source having a plurality of unit cells connected to the output stages, each of the plurality of unit cells comprising a current source. The digitally controlled current source is configured for driving the output stages with respective driving currents originating from the associated current source in each of the plurality of unit cells, in dependence of one or more input signals. The digitally controlled current source further comprises a current diversion path in each of the plurality of unit cells for providing a diversion current to a voltage source having a voltage lower than drain/collector terminals of transistors provided in the CG/CB configured output stages.
    Type: Application
    Filed: March 19, 2021
    Publication date: May 11, 2023
    Applicant: Technische Universiteit Delft
    Inventors: Leonardus Cornelis Nicolaas De Vreede, Yiyu Shen, Seyed Morteza Alavi
  • Publication number: 20230139209
    Abstract: An RF transmitter (1) having a gate-segmented power output stage (2) and a digital driver (5). The gate-segmented power output stage (2) includes a field-effect transistor with a plurality of gate fingers (32) and drain fingers (31) that define a gate periphery. The field-effect transistor comprises a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery, and that each have a respective power output stage segment input (4). The digital driver (5) has control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), and is configured for individually switching each of the power output stage segments (3) between an on mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).
    Type: Application
    Filed: February 5, 2021
    Publication date: May 4, 2023
    Applicant: Technische Universiteit Delft
    Inventors: Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi, Robert Jan Bootsman, Mohammad Reza Beikmirza, Dieuwert Peter Nicolaas Mul, Rob Heeres, Freerk van Rijs
  • Patent number: 10892935
    Abstract: A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3rd-order and 5th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 12, 2021
    Assignee: Technische Universiteit Delft
    Inventors: Mohammed Reza Mehrpoo, Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi
  • Patent number: 10644656
    Abstract: A wideband, frequency agile, radio frequency digital-to-analog converter (RF-DAC) based phase modulator includes first, second, and third RF-DACs, each configured to upconvert an input I/Q digital baseband signal pair to a local oscillator (LO) frequency but with the first RF-DAC being driven by a first set of LO clocks, the second RF-DAC being driven by a second set of LO clocks that is forty-five degrees out of phase with respect to the first set of LO clocks, and the third RF-DAC being driven by a third set of LO clocks that is a further forty-five degrees out of phase with respect to the second set of LO clocks. First, second, and third upconverted analog signals produced by the first, second, and third RF-DACs are combined to reinforce the fundamental LO component while canceling 3rd-order and 5th-order LO harmonics.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 5, 2020
    Assignee: Technische Universiteit Delft
    Inventors: Leonardus Cornelius Nicolaas de Vreede, Seyed Morteza Alavi, Mohammedreza Mehrpoo, Mikhail Evgenyevich Polushkin, Mohsen Hashemi, Yiyu Shen
  • Publication number: 20200112471
    Abstract: A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3rd-order and 5th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.
    Type: Application
    Filed: May 30, 2018
    Publication date: April 9, 2020
    Applicant: Technische Universiteit Delft
    Inventors: Mohammed Reza Mehrpoo, Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi
  • Publication number: 20190207565
    Abstract: A wideband, frequency agile, radio frequency digital-to-analog converter (RF-DAC) based phase modulator includes first, second, and third RF-DACs, each configured to upconvert an input I/Q digital baseband signal pair to a local oscillator (LO) frequency but with the first RF-DAC being driven by a first set of LO clocks, the second RF-DAC being driven by a second set of LO clocks that is forty-five degrees out of phase with respect to the first set of LO clocks, and the third RF-DAC being driven by a third set of LO clocks that is a further forty-five degrees out of phase with respect to the second set of LO clocks. First, second, and third upconverted analog signals produced by the first, second, and third RF-DACs are combined to reinforce the fundamental LO component while canceling 3rd-order and 5th-order LO harmonics.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 4, 2019
    Applicant: Technische Universiteit Delft
    Inventors: Leonardus Cornelius Nicolaas de Vreede, Seyed Morteza Alavi, Mohammedreza Mehrpoo, Mikhail Evgenyevich Polushkin, Mohsen Hashemi, Yiyu Shen