Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Abstract: Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: A method for manufacturing a housing of an electronic device includes the following steps. An area not to be etched is shielded and an etching area is exposed. The etching area is etched by photolithography and forming a plurality of heat dissipation holes of nanometer scale in the etching area. The area not to be etched is cleaned for removing the shielding.

Abstract: A method for manufacturing composite of resin and other materials includes the following steps. A shaped piece made by materials different with resin is provided, and is degreased and cleaned. A resist layer with a lot of location holes is formed on the surface of the heterogeneous member by nano-imprint lithography, and a lot of small holes are formed on the surface of the heterogeneous member while the resist layer is removed. Then the heterogeneous member is inserted in an injection mold, and molten crystalline thermoplastic resin is injected into the mold, thus the resin embedded into the holes and bonding with the shaped piece. The method is environmentally friendly and suitable for mass production.

Abstract: A method for manufacturing a housing of an electronic device includes the following steps. An area not to be etched is shielded and an etching area is exposed. The etching area is etched by photolithography and forming a plurality of heat dissipation holes of nanometer scale in the etching area. The area not to be etched is cleaned for removing the shielding.

Abstract: An electronic device includes a housing, a mother board received in the housing, and a plurality of heat-generating members received in the housing. A dissipation area is formed in the housing, and a plurality of dissipation holes are defined in an outer surface of the dissipation area. Each dissipation hole is in a nanometer scale. The disclosure also supplies a method for manufacturing a housing of the electronic device.

Abstract: A method for surface treating an aluminum alloy workpiece having zinc and magnesium includes: providing the aluminum alloy workpiece; polishing the aluminum alloy to achieve a mirror effect; degreasing the aluminum alloy workpiece; stripping a black film formed on the aluminum alloy workpiece; anodizing the aluminum alloy workpiece in an anodizing solution which includes acidic solution and an additive with a concentration of 0.5 mg/L to 25 g/L to form an oxidation film on the surface of the aluminum alloy workpiece, wherein the additive including at least one compound selected from a group consisting of adipic acid, 1,2,3-Benzotriazole, oxalic acid, sodium malate, and glycerin; and sealing the aluminum alloy workpiece. This disclosure further provides an anodizing solution applied in the method for surface treating an aluminum alloy workpiece and a method for anodizing the aluminum alloy workpiece using the same.

Abstract: A method for manufacturing composite of resin and other materials includes the following steps. A shaped piece made by materials different with resin is provided, and is degreased and cleaned. A resist layer with a lot of location holes is formed on the surface of the heterogeneous member by nano-imprint lithography, and a lot of small holes are formed on the surface of the heterogeneous member while the resist layer is removed. Then the heterogeneous member is inserted in an injection mold, and molten crystalline thermoplastic resin is injected into the mold, thus the resin embedded into the holes and bonding with the shaped piece. The method is environmentally friendly and suitable for mass production.

Abstract: An electronic device includes a housing, a mother board received in the housing, and a plurality of heat-generating members received in the housing. A dissipation area is formed in the housing, and a plurality of dissipation holes are defined in an outer surface of the dissipation area. Each dissipation hole is in a nanometer scale. The disclosure also supplies a method for manufacturing a housing of the electronic device.

Abstract: A speaker includes a holder forming a hollow space, a magnetic system received in the hollow space, a suspension assembled with the holder and defining a supporting portion, a pair of fixing portions far away from the supporting portion and fixed on the holder, and a plurality of arm portions connecting the supporting portion and the fixing portions, respectively. The arm portions defines a pair of outer arm portions protruded outwardly from the circumference of two ends of the supporting portion and a pair of inner arm portions extending from the circumference of said two ends of the supporting portion and set in space with respect to the inner arm portions, respectively.

Abstract: A housing includes a main body having an interface and a plastic portion molded on the interface. The main body defines a nanostructure in the interface. The nanostructure includes a plurality of regular, repeating units. A pitch between the adjacent units is in the range from 10 nanometers to 500 nanometers. A height of each unit is in the range from 10 nanometers to 100 nanometers. A surface roughness of the nanostructure is in the range from 1 nanometer to 10 nanometers.