Patents by Inventor Shadi A. DAYEH

Shadi A. DAYEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240131339
    Abstract: A flexible electrode array with hundreds or thousands channels for clinical use includes an array of at least hundreds of electrodes on a flexible biocompatible polymer substrate. Perfusion through holes are provided through the substrate. Individual elongate leads connect to each of the electrodes, the elongate lead connections being supported by the flexible biocompatible polymer substrate and extending away from the array. Flexible biocompatible polymer insulates the individual elongate lead connections and supporting the array. An interposer with individual channel connections is conductively bonded to the individual elongate lead connections. Sterile bag packaging encloses a portion of the interposer, where the outer side of the package including the array and individual elongate lead is sterile while the inner side of the packaging is non-sterile. The portion interposer inside the package is configured to connect to a circuit board within the packaging.
    Type: Application
    Filed: March 10, 2022
    Publication date: April 25, 2024
    Inventors: Shadi A. Dayeh, Youngbin Tchoe, Andrew M. Bourhis
  • Publication number: 20230271320
    Abstract: A flexible thin film transistor tactile sensor includes a piezoelectric semiconductor thin film channel of material whose conductivity can be electrostatically controlled connected with source and drain metals and sandwiched between bottom and top thin film insulators and at least one of a bottom and top gate metal, the sensor being supported on a flexible substrate. The piezoelectric property of the used material transduces pressure to electronic charge. The semiconductor property of the used material permits electrostatic modulation of the conductivity in TFT device architecture such that the device can be switched on and off. Transistor action provides gain for input signals, i.e., a modulation of the gate voltage induces strong current change between the source and drain, which can be leveraged to amplify the response to input pressure. The transistor forms the basis for sensor arrays, which are readily scalable to large size.
    Type: Application
    Filed: August 4, 2021
    Publication date: August 31, 2023
    Inventors: Shadi A. DAYEH, Hongseok OH
  • Patent number: 11363979
    Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 21, 2022
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Renjie Chen, Sang Heon Lee, Ren Liu, Yun Goo Ro, Atsunori Tanaka, Yoontae Hwang
  • Patent number: 11233142
    Abstract: Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plurality of widths and are selected to lead to the separate turn-on voltage thresholds for the largest, intermediate and smallest widths of the MIS HEMT fins flatten the transconductance gm curve over an operational range of gate source voltage.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 25, 2022
    Assignee: The Regents of the Unverslty of California
    Inventors: Shadi A. Dayeh, Woojin Choi, Renjie Chen, Atsunori Tanaka, Ren Liu
  • Publication number: 20210371987
    Abstract: A method for fabricating a Pt nanorod electrode array sensor device includes forming planar metal electrodes on a flexible film, co-depositing Pt alloy on the planar metal electrodes via physical vapor deposition, and dealloying the Pt alloy to etch Pt nanorods from the deposited Pt alloy. A Pt nanorod electrode sensor device includes a plurality of porous Pt nanorods on a planar metal electrode forming a sensor electrode. The planar metal electrode is on a flexible substrate. An electrode lead on the flexible substrate extends away from the planar metal electrode. Insulation is around porous Pt nanorods an upon the electrode lead.
    Type: Application
    Filed: November 7, 2019
    Publication date: December 2, 2021
    Inventors: Shadi A. Dayeh, Mehran Ganji
  • Patent number: 11056517
    Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 6, 2021
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy
  • Publication number: 20210093246
    Abstract: A nanowire electrode array has a plurality of vertical nanowires extending from a substrate, each of the nanowires including a core of unitary first dielectric material that also covers the substrate and is unitary with the substrate. Each core has a sharp sub-100 nm diameter tip and a wider base, electrode leads on sidewalls to the tip of the nanowire, and second dielectric covering the electrode leads. The tips in the array can penetrate individual cells in cell culture, such as a mini-brain culture. The substrate can include a window for simultaneous optical imaging and electrophysiological recording.
    Type: Application
    Filed: May 8, 2019
    Publication date: April 1, 2021
    Inventors: Shadi DAYEH, Ren LIU, Youngbin TCHOE
  • Patent number: 10856764
    Abstract: A preferred conformal penetrating multi electrode array includes a plastic substrate that is flexible enough to conform to cortical tissue. A plurality of penetrating semiconductor micro electrodes extend away from a surface of the flexible substrate and are stiff enough to penetrate cortical tissue. Electrode lines are encapsulated at least partially within the flexible substrate and electrically connected to the plurality of penetrating semiconductor microelectrodes. The penetrating semiconductor electrodes preferably include pointed metal tips. A preferred method of fabrication permits forming stiff penetrating electrodes on a substrate that is very flexible, and providing electrical connection to electrode lines within the substrate.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: December 8, 2020
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Farid Azzazy, Sang Heon Lee
  • Publication number: 20200295170
    Abstract: Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plurality of widths and are selected to lead to the separate turn-on voltage thresholds for the largest, intermediate and smallest widths of the MIS HEMT fins flatten the transconductance gm curve over an operational range of gate source voltage.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 17, 2020
    Inventors: Shadi A. Dayeh, Woojin Choi, Renjie Chen, Atsunori Tanaka, Ren Liu
  • Patent number: 10679964
    Abstract: A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 9, 2020
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Renjie Chen
  • Publication number: 20190021619
    Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 24, 2019
    Inventors: Shadi A. Dayeh, Renjie Chen, Sang Heon Lee, Ren Liu, Yun Goo Ro, Atsunori Tanaka, Yoontae Hwang
  • Publication number: 20180040649
    Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
    Type: Application
    Filed: March 10, 2016
    Publication date: February 8, 2018
    Inventors: Shadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy
  • Publication number: 20170317050
    Abstract: A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.
    Type: Application
    Filed: November 3, 2015
    Publication date: November 2, 2017
    Inventors: Shadi A. Dayeh, Renjie Chen
  • Publication number: 20170231518
    Abstract: A preferred conformal penetrating multi electrode array includes a plastic substrate that is flexible enough to conform to cortical tissue. A plurality of penetrating semiconductor micro electrodes extend away from a surface of the flexible substrate and are stiff enough to penetrate cortical tissue. Electrode lines are encapsulated at least partially within the flexible substrate and electrically connected to the plurality of penetrating semiconductor microelectrodes. The penetrating semiconductor electrodes preferably include pointed metal tips. A preferred method of fabrication permits forming stiff penetrating electrodes on a substrate that is very flexible, and providing electrical connection to electrode lines within the substrate.
    Type: Application
    Filed: August 7, 2015
    Publication date: August 17, 2017
    Inventors: Shadi A. DAYEH, Farid AZZAZY, Sang Heon LEE
  • Patent number: 9024295
    Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire photodetectors include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 5, 2015
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Yu-Hwa Lo, Arthur Zhang, David Aplin, Lingquan Wang, Shadi Dayeh, Xin Yu Bao
  • Patent number: 8440997
    Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: May 14, 2013
    Assignee: The Regents of the University of California
    Inventors: Deli Wang, Cesare Soci, Yu-Hwa Lo, Arthur Zhang, David Aplin, Lingquan Wang, Shadi Dayeh, Xin Yu Bao
  • Publication number: 20100295019
    Abstract: A practical ID nanowire photodetector with high gain that can be controlled by a radial electric field established in the ID nanowire. A ID nanowire photodetector device of the invention includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to the nanowire inhibits photo-carrier recombination, thus enhancing the photocurrent response. The invention further provides circuits of ID nanowire photodetectors, with groups of photodetectors addressed by their individual ID nanowires electrode contacts. The invention also provides a method for placement of ID nanostructures, including nanowires, with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of ID nanostructures.
    Type: Application
    Filed: February 26, 2008
    Publication date: November 25, 2010
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Deli Wang, Cesare Soci, Yu-Hwa Lo, Arthur Zhang, David Aplin, Lingquan Wang, Shadi Dayeh, Xin Yu Bao