Patents by Inventor Shadi Khasawneh

Shadi Khasawneh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11593154
    Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Ahmad Samih, Rajshree Chabukswar, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, Monica Gupta, Christine M. Lin
  • Publication number: 20220197856
    Abstract: In one embodiment, a processor includes: at least one configuration register to store configuration information for a hardware resource including a control circuit to configure the hardware resource based at least in part on the configuration information; a performance monitor to maintain performance information during execution of an application on the processor; and a controller coupled to the at least one configuration register. The controller may dynamically provide the configuration information to the at least one configuration register based at least in part on the performance information, and the control circuit is to adjust a performance tuning of the hardware resource according to the configuration information. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: SHADI KHASAWNEH, SABINE FRANCIS, HANNA ALAM, ALEXANDER GENDLER
  • Publication number: 20200201671
    Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: AHMAD SAMIH, RAJSHREE CHABUKSWAR, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, MONICA GUPTA, CHRISTINE M. LIN