Abstract: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a memory device with staggered isolation regions and methods of manufacture. The structure includes: a source line; a gate structure adjacent to the source line; and isolation structures on opposing sides of the source line. The isolation structures on a first side of the source line are laterally offset from the isolation structures on a second side of the source line.

Abstract: An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.

Abstract: An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.