Abstract: Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.

Abstract: Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Abstract: An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating layer between the first metal layer and the second metal layer. First vias and second vias are formed in the insulating layer. The first vias have a first aspect ratio greater than a second aspect ratio of the second vias. A barrier-less metal partially fills the first vias and fills the second vias. A pure metal fills a remainder of the first vias.

Abstract: Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

Abstract: Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.

Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

Abstract: Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6.

Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

Abstract: An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.

Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

Abstract: Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon.

Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.