Abstract: A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.

Abstract: A substrate is provided. The substrate includes a base, a semiconductor layer over the base, and an insulator layer between the base and the semiconductor layer. The semiconductor layer has a first semiconductor layer portion having a first thickness, a second semiconductor layer portion having a second thickness, and a third semiconductor layer portion having a third thickness, and the first thickness, the second thickness, and the third thickness are different from each other.

Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

Abstract: Disclosed are a high-density stacked capacitor and an associated formation method. The high-density stacked capacitor includes: first and second terminals; and a stack of parallel-connected capacitors between the terminals. The stack includes a first capacitor (e.g., a planar transistor-type capacitor) including: a channel region positioned laterally between source/drain regions, which are connected to the first terminal; and front and back gates, which are above and below the channel region and connected to the second terminal. The stack also includes at least one additional capacitor (e.g., a metal-oxide-metal capacitor (MOMCAP)) aligned above the front gate of the first capacitor in a back end of the line (BEOL) metal level. Optionally, the capacitor includes multiple additional capacitors aligned above the front gate and stacked vertically one above the other in different BEOL metal levels.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor, and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor. At least one capacitance in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.

Abstract: Disclosed are a semiconductor structure and method of forming the semiconductor structure. The semiconductor structure includes a high-density stacked capacitor and, particularly, a stack of capacitors connected in parallel between two nodes. The stack includes a diode-type capacitor (also referred to herein as a PN junction capacitor) within a semiconductor substrate. In different embodiments, the diode-type capacitor has different in-substrate well configurations. The stack also includes a transistor-type capacitor (e.g., a metal oxide semiconductor capacitor (MOSCAP)) on an insulator layer aligned above the diode-type capacitor. Optionally, the stack also includes at least one additional capacitor (e.g., at metal-oxide-metal capacitor (MOMCAP)) on a dielectric layer aligned above the transistor-type capacitor (e.g., in one or more back end of the line (BEOL) metal levels).

Abstract: A beamforming front end (BFFE) for a receiver performs beamforming without needing to perform phase-shifting on each of a plurality of received signals. The BFFE comprises first variable gain amplifiers (VGAs) that respectively amplify the received signals by first gain values and second VGAs that respectively amplify the received signals by second gain values. Outputs of the first VGAs are combined into a first combined signal, and outputs of the second VGAs are combined into a second combined signal. The first and second combined signals are then used to produce an output signal corresponding to phase-shifting the received signals by amounts corresponding to the respective first and second gain values and then summing the results of the phase shifting. The output signal may be produced by mixing the first combined signal with an in-phase local oscillator signal and mixing the second combined signal with a quadrature local oscillator signal.

Abstract: A transceiver front-end (FE) includes a receiver from an I/O pad to an amplifier (e.g., a low noise amplifier (LNA)) and a transmitter from the I/O pad to another amplifier (e.g., a power amplifier (PA)). The receiver further includes a variable inductor connected at one end to the I/O pad and connectable at the opposite end to ground by a switch. The LNA is connected to a node between portions of the inductor. When receiving, the switch is opened so the inductor exhibits low inductance for LNA impedance matching. When transmitting, the switch is closed so the inductor exhibits high inductance for blocking leakage to the LNA. Additionally, or alternatively, the transmitter includes a variable capacitor connected to the I/O pad. When receiving, the capacitor is programmed to exhibit low capacitance for optimal LNA performance. When transmitting, the capacitor is programmed to exhibit high capacitance for optimal PA performance.

Abstract: A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.

Abstract: A differential power amplifier circuit, including: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier, coupled in parallel with the first differential power amplifier, including a plurality of multi-gate transistors.

Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

Abstract: A system for migrating a non-tenant-aware local application to a tenant-aware cloud application environment is disclosed to migrate individual modules of the application to instances of the cloud by grouping the modules via common characteristics in partition groups. By grouping modules together by partition group before migrating the modules to cloud instances, modules that share resources can be placed in closer logical proximity to one another in the cloud, modified, or deleted to optimize performance. The information from these modules is processed to create a visualization graph representing information on the cloud. The visualization graph is preferably multilayered so it can display information from different hierarchical layers of a cloud instance.

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

Abstract: A substrate is provided. The substrate includes a base, a semiconductor layer over the base, and an insulator layer between the base and the semiconductor layer. The semiconductor layer has a first semiconductor layer portion having a first thickness, a second semiconductor layer portion having a second thickness, and a third semiconductor layer portion having a third thickness, and the first thickness, the second thickness, and the third thickness are different from each other.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor, and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor. At least one capacitance in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.

Abstract: A system for migrating a non-tenant-aware local application to a tenant-aware cloud application environment is disclosed to migrate individual modules of the application to instances of the cloud by grouping the modules via common characteristics in partition groups. By grouping modules together by partition group before migrating the modules to cloud instances, modules that share resources can be placed in closer logical proximity to one another in the cloud, modified, or deleted to optimize performance. The information from these modules is processed to create a visualization graph representing information on the cloud. The visualization graph is preferably multilayered so it can display information from different hierarchical layers of a cloud instance.

Abstract: An accurate monitoring system for a multi-tenant system monitors each data stream of the multi-tenant system and determines the identity of the tenant using each of the data streams, and the application that the tenant is accessing. Aspects of each data stream are aggregated by a bucket aggregator to track and record trends for each tenant and/or each application. The aggregated data could be filtered, sorted, and reported for accurate subscription billing for each of the tenants and/or applications within a multi-tenant system.

Abstract: A system for migrating a non-tenant-aware local application to a tenant-aware cloud application environment is disclosed to migrate individual modules of the application to instances of the cloud by grouping the modules via common characteristics in partition groups. By grouping modules together by partition group before migrating the modules to cloud instances, modules that share resources can be placed in closer logical proximity to one another in the cloud, modified, or deleted to optimize performance. The information from these modules is processed to create a visualization graph representing information on the cloud. The visualization graph is preferably multilayered so it can display information from different hierarchical layers of a cloud instance.

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

Abstract: A system for migrating a non-tenant-aware local application to a tenant-aware cloud application environment is disclosed to migrate individual modules of the application to instances of the cloud by grouping the modules via common characteristics in partition groups. By grouping modules together by partition group before migrating the modules to cloud instances, modules that share resources can be placed in closer logical proximity to one another in the cloud, modified, or deleted to optimize performance. The information from these modules is processed to create a visualization graph representing information on the cloud. The visualization graph is preferably multilayered so it can display information from different hierarchical layers of a cloud instance.