Patents by Inventor Shagun Dusad

Shagun Dusad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113678
    Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 4, 2024
    Inventors: Shagun Dusad, Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad
  • Publication number: 20240072820
    Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sai Aditya Nurani, Rishi Soundararajan, Nithin Gopinath, Visvesvaraya Pentakota, Shagun Dusad
  • Patent number: 11916567
    Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
  • Patent number: 11888459
    Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad
  • Patent number: 11881867
    Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
  • Patent number: 11831283
    Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: November 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vajeed Nimran, Raja Sekhar, Sandeep Oswal, Shagun Dusad
  • Patent number: 11489515
    Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: November 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eeshan Miglani, Shagun Dusad
  • Patent number: 11424758
    Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: August 23, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
  • Publication number: 20220247421
    Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 4, 2022
    Inventors: Visvesvaraya Appala Pentakota, Srinivas Kumar Reddy Naru, Chirag Shetty, Eeshan Miglani, Neeraj Shrivastava, Narasimhan Rajagopal, Shagun Dusad
  • Publication number: 20220247420
    Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
    Type: Application
    Filed: September 7, 2021
    Publication date: August 4, 2022
    Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
  • Publication number: 20220173711
    Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
    Type: Application
    Filed: September 1, 2021
    Publication date: June 2, 2022
    Inventors: Shagun Dusad, Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad
  • Publication number: 20220173710
    Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first parasitic capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second parasitic capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
    Type: Application
    Filed: August 25, 2021
    Publication date: June 2, 2022
    Inventors: Shagun Dusad, Vysakh Karthikeyan, Naveen Mahadev, Rafi Mahammad
  • Publication number: 20220131551
    Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Inventors: Sai Aditya Krishnaswamy NURANI, Joseph Palackal MATHEW, Prasanth K., Visvesvaraya Appala PENTAKOTA, Shagun DUSAD
  • Patent number: 11309902
    Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 19, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
  • Patent number: 11277145
    Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
  • Patent number: 11239851
    Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Anand Jerry George, Shagun Dusad, Visvesvaraya Appala Pentakota
  • Publication number: 20210399720
    Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Inventors: Eeshan MIGLANI, Shagun DUSAD
  • Publication number: 20210328595
    Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Inventors: Sai Aditya Krishnaswamy NURANI, Joseph Palackal MATHEW, Prasanth K, Visvesvaraya Appala PENTAKOTA, Shagun DUSAD
  • Patent number: 11139799
    Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eeshan Miglani, Shagun Dusad
  • Publication number: 20210258018
    Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: Shagun DUSAD, Chirag Chandrahas SHETTY, Visvesvaraya Appala PENTAKOTA