Abstract: A standard cell layout for a multiple input logic gate includes first through fourth parallel gate electrodes disposed over first and second active regions. The first and second gate electrodes are disposed on a first side of a first axis at first and second distances, respectively, from the first axis, and the third and fourth gate electrodes are disposed on a second side of the first axis at third and fourth distances, respectively, from the first axis. The first distance is greater than the second distance and the fourth distance is greater than the third distance. The third and fourth gate electrodes form a mirror image of the first and second gate electrodes about the first axis.