Abstract: A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

Abstract: A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

Abstract: A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

Abstract: A switch having a higher speed port, one or more slower speed ports, a larger buffer memory and numerous larger counters to achieve higher speed and longer range of communication. In one embodiment a larger switch having a larger buffer memory and larger counters connects to a smaller switch having a smaller buffer memory and smaller counters, the larger switch practically expanding the buffer memory and counters in the smaller switch. A combination of several counters can also avoid buffer overrun in any switches in the frame flow path due to the mismatch between the counter capabilities, the limitations of physical buffer spaces or the mismatch between transmission speeds. In another embodiment, the buffer spaces in several switches can be aggregated or cascaded along a frame path so that there are enough credits to maintain a high-speed transmission over a long distance.