Abstract: Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., RF semiconductor devices) on the insulator layer. Each method includes at least: attaching a temporary carrier above back end of the line (BEOL) metal levels, which are over an interlayer dielectric layer covering one or more semiconductor devices; removing at least a portion of a semiconductor handler substrate, which is below the semiconductor device(s) and separated therefrom by an insulator layer; replacing the semiconductor handler substrate with a replacement handler substrate made of an electrically insulative molding compound; and removing the temporary carrier.

Abstract: Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., RF semiconductor devices) on the insulator layer. Each method includes at least: attaching a temporary carrier above back end of the line (BEOL) metal levels, which are over an interlayer dielectric layer covering one or more semiconductor devices; removing at least a portion of a semiconductor handler substrate, which is below the semiconductor device(s) and separated therefrom by an insulator layer; replacing the semiconductor handler substrate with a replacement handler substrate made of an electrically insulative molding compound; and removing the temporary carrier.

Abstract: Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.

Abstract: A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.

Abstract: A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.

Abstract: A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.

Abstract: A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.

Abstract: A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.

Abstract: Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.

Abstract: Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.

Abstract: A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies.

Abstract: Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching.

Abstract: A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system is disclosed. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies. A method for determining blur, focus and exposure dose error in lithographic imaging is also disclosed.

Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated.

Abstract: The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.

Abstract: The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. Considering that the facet in the prior art is due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.

Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Abstract: A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies.

Abstract: The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the condition that the product of surface area and transmission of the electrical field strength is the same for all of the portions. Then, frequency doubling occurs due to vanishing zero order diffraction orders and in the case of high-transition attenuated phase-shift masks a large first order diffraction amplitude reveals an even an improved as compared with conventional phase-shift masks. Two-dimensional matrix-like structures particularly on attenuated or halftone phase-shift masks can be arranged to image high-density patterns on a semiconductor wafer. The duty cycles of pattern matrices can be chosen being different from one in two orthogonal directions nevertheless leading to frequency doubling.

Abstract: Non-uniformity and image shortening are substantially reduced in an image printed on a substrate using a photolithographic mask in which the mask pattern includes at least one lines and spaces array adjacent to at least one clear region. At least one line feature is incorporated within the clear region of the mask pattern and is disposed in proximity to the lines and spaces array. The line feature has a line width that is smaller than a minimum resolution of the optical projection system. The image is printed by illuminating the photolithographic mask and projecting light transmitted through the photolithographic mask onto the substrate using the optical projection system.