Abstract: A power system is presented. The power system includes a first converter including a first output terminal a first control unit coupled to the first converter, a second converter including a second output terminal, where the second converter is coupled in parallel to the first converter, and a second control unit coupled to the second converter. The second control unit is configured to measure a plurality of phase currents at the second output terminal, determine a harmonic current transmitted by the second converter based on single phase current of the plurality of measured phase currents, and change a time-period of at least one switching cycle of a carrier wave of the second converter based on the determined harmonic current to synchronize with a carrier wave of the first converter.

Abstract: A power system is disclosed. The power system includes a first power generating unit. The first power generating unit includes a first power converting subunit and a first control unit coupled to the first power converting subunit, where the first control unit is configured to regulate a voltage of the first power generating unit. The power system further includes a second power generating unit coupled to the first power generating unit and a load, where the second power generating unit includes a second power converting subunit and a second control unit coupled to the second power converting subunit, wherein the second control unit is configured to control a current of the second power generating unit to share a quantity of electrical output current flowing through the load among the first and second power generating units.

Abstract: Systems and methods for determining an out of balance condition of a washing machine are provided. In particular, a plurality of angular positions of a motor associated with a washing machine can be determined. The washing machine can include a wash tub, and a wash basket rotatably mounted within the wash tub. The motor is configured to rotate the wash basket within said wash tub. Data indicative of at least a single phase of motor current being applied to the motor can be obtained while the wash basket rotates. The data can be spatially sampled over at least a subset of the plurality of angular positions of the motor. An out of balance condition associated with the washing machine can be determined based at least in part on the sampled data.

Abstract: A heat-assisted magnetic recording (HAMR) medium has a multilayered or laminated heat-sink structure. The laminated heat-sink structure includes a first heat-sink layer and a RuAl—X thermal barrier layer between the medium substrate and the first heat-sink layer. The laminated heat-sink structure may include a second heat-sink layer may between the substrate and the RuAl—X thermal barrier layer. In the RuAl—X thermal barrier layer, X is selected from C and one or more oxides of Si, Ti, W, Zr and Hf. The HAMR medium with the laminated heat-sink structure reduces the amount of required laser current as compared to a similar HAMR medium with a conventional single heat-sink layer of the same thickness, while also slightly improving magnetic properties and recording performance.

Abstract: Systems and methods for determining an out of balance condition of a washing machine are provided. In particular, a plurality of angular positions of a motor associated with a washing machine can be determined. The washing machine can include a wash tub, and a wash basket rotatably mounted within the wash tub. The motor is configured to rotate the wash basket within said wash tub. Data indicative of at least a single phase of motor current being applied to the motor can be obtained while the wash basket rotates. The data can be spatially sampled over at least a subset of the plurality of angular positions of the motor. An out of balance condition associated with the washing machine can be determined based at least in part on the sampled data.

Abstract: A driver unit for an interior permanent magnet motor (IPM) is presented. The driver unit includes sensor electronics configured to sense a phase voltage corresponding to one or more phase terminals of the IPM motor to generate a corresponding phase voltage signal. The driver unit further includes a controller electrically coupled to the sensor electronics and configured to extract one or more triplen harmonics of an order of a ninth harmonic and higher than the ninth harmonic of a fundamental frequency of the phase voltage signal corresponding to the one or more phase terminals. The controller is further configured to determine an angular position of a rotor of the IPM motor based on the extracted one or more triplen harmonics. Related motor assembly and method for controlling the IPM motor are also presented.

Abstract: Systems and methods of presentation of a response related to a dispute element are herein disclosed. A request from a device associated with a first user is received. The request including a request to access a customer service page with information related to a transaction between the first user and a second user. Transaction characteristics of the transaction and user characteristics of the first user may be identified. A dispute element associated with the transaction is detected based on the transaction characteristics and the user characteristics of the first user. A response related to the detected dispute element is generated. Presentation of the response related to the detected dispute element is caused.

Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.

Abstract: The present invention relates to novel bisazo dyes, a process for their preparation and their use for dyeing and/or printing substrates.

Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.

Abstract: Systems and methods of presentation of a response related to a dispute element are herein disclosed. A request from a device associated with a first user is received. The request including a request to access a customer service page with information related to a transaction between the first user and a second user. Transaction characteristics of the transaction and user characteristics of the first user may be identified. A dispute element associated with the transaction is detected based on the transaction characteristics and the user characteristics of the first user. A response related to the detected dispute element is generated. Presentation of the response related to the detected dispute element is caused.

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Abstract: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

Abstract: Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Abstract: A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for comparing search data with content data stored in a ternary content addressable memory (TCAM) unit, includes a first static logic gate for comparing a first content data with a first search data, and a second static logic gate coupled to the first static logic gate for comparing a second content data with a second search data. The content data comprises the first content data and the second content data and the search data comprises the first search data and the second search data. The first static logic gate forwards a signal for disabling the second static logic gate if the first content data does not match with the first search data.

Abstract: A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM), includes a storage unit for storing a portion of content data, and a match module for comparing the portion of the content data with a respective portion of search data received by the match module. The match module includes a first static logic gate associated with a first half of the storage unit storing a sub-portion of the portion of the content data, and a second static logic gate associated with a second half of the storage unit. The first static logic gate forwards a signal for disabling the second static logic gate if the sub-portion of the portion of the content data does not match with a respective sub-portion of the portion of the search data.