Patents by Inventor Shahin Mehdizad Taleie
Shahin Mehdizad Taleie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250062754Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.Type: ApplicationFiled: August 14, 2023Publication date: February 20, 2025Inventors: Shahin MEHDIZAD TALEIE, Dongwon SEO, Bhushan Shanti ASURI, Ibrahim Ramez CHAMAS, Huan WANG, Zhiheng WANG, Reza RODD
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Publication number: 20240204795Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.Type: ApplicationFiled: December 20, 2022Publication date: June 20, 2024Inventors: Ashok SWAMINATHAN, Nitz SAPUTRA, Negar RASHIDI, Shahin MEHDIZAD TALEIE, Chinmaya MISHRA, Dongwon SEO, Jong Hyeon PARK, Sang-June PARK
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Patent number: 11728822Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.Type: GrantFiled: June 28, 2021Date of Patent: August 15, 2023Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Dongwon Seo, Ashok Swaminathan, Gurkanwal Singh Sahota, Andrew Weil, Haibo Fei
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Patent number: 11621716Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.Type: GrantFiled: September 22, 2021Date of Patent: April 4, 2023Assignee: QUALCOMM IncorporatedInventors: Parisa Mahmoudidaryan, Nitz Saputra, Dongwon Seo, Shahin Mehdizad Taleie
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Publication number: 20230097708Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.Type: ApplicationFiled: September 22, 2021Publication date: March 30, 2023Inventors: Parisa MAHMOUDIDARYAN, Nitz SAPUTRA, Dongwon SEO, Shahin MEHDIZAD TALEIE
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Publication number: 20220416804Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Inventors: Shahin MEHDIZAD TALEIE, Dongwon SEO, Ashok SWAMINATHAN, Gurkanwal Singh SAHOTA, Andrew WEIL, Haibo FEI
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Patent number: 11387933Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a downlink control message from a base station indicating a modulation and coding scheme (MCS) associated with an uplink transmission, a number of layers associated with the uplink transmission, or both. The UE may determine to adjust (for example, reduce) a first number of bits based on the MCS, the number of layers, or both. The first number of bits may include an effective number of bits (ENOB) supported at a digital-to-analog converter (DAC) of the UE, a number of bits (NOB) supported at a transmission front end (TxFE) component of the UE, or both. The UE may transmit the uplink transmission to the base station according to the adjusted first number of bits.Type: GrantFiled: January 31, 2020Date of Patent: July 12, 2022Assignee: QUALCOMM IncorporatedInventors: Igor Gutman, Shahin Mehdizad Taleie, Oren Matsrafi, Ronen Greenberger, Gal Keret, Yossi Waldman, Gideon Shlomo Kutz
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Patent number: 11184018Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.Type: GrantFiled: November 2, 2020Date of Patent: November 23, 2021Assignee: QUALCOMM IncorporatedInventors: Xilin Liu, Parisa Mahmoudidaryan, Shahin Mehdizad Taleie, Negar Rashidi, Dongwon Seo
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Publication number: 20210242958Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a downlink control message from a base station indicating a modulation and coding scheme (MCS) associated with an uplink transmission, a number of layers associated with the uplink transmission, or both. The UE may determine to adjust (for example, reduce) a first number of bits based on the MCS, the number of layers, or both. The first number of bits may include an effective number of bits (ENOB) supported at a digital-to-analog converter (DAC) of the UE, a number of bits (NOB) supported at a transmission front end (TxFE) component of the UE, or both. The UE may transmit the uplink transmission to the base station according to the adjusted first number of bits.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Igor Gutman, Shahin Mehdizad Taleie, Oren Matsrafi, Ronen Greenberger, Gal Keret, Yossi Waldman, Gideon Shlomo Kutz
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Publication number: 20200336541Abstract: Various aspects enable sensor data to be obtained from vehicles. Various aspects may enable data gathered by sensors of vehicles to be obtained by a data agency server and made available to third party client devices. In various aspects, a data agency server may direct a vehicle to drive from the vehicle's current location to a different specific location to gather a type of data. In some aspects, the type of data may be peripheral data that is not associated with driving operations of a vehicle. In some aspects, a data agency server may indicate one or more attributes of collection for the vehicle to utilize in gathering data. In some aspects, an attribute of collection may set a condition of the vehicle and/or the sensor utilized in gathering data. In some embodiments, vehicle owners/operators may be compensated for their vehicles being utilized to obtain data.Type: ApplicationFiled: April 16, 2019Publication date: October 22, 2020Inventors: Mohammadhossein Naderi Alizadeh, Shahin Mehdizad Taleie
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Patent number: 10797720Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.Type: GrantFiled: March 28, 2019Date of Patent: October 6, 2020Assignee: QUALCOMM IncorporatedInventors: Eunyung Sung, Nitz Saputra, Behnam Sedighi, Ashok Swaminathan, Honghao Ji, Shahin Mehdizad Taleie, Dongwon Seo
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Patent number: 10686476Abstract: An RF-DAC transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.Type: GrantFiled: May 20, 2019Date of Patent: June 16, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Nitz Saputra, Chen Jiang, Behnam Sedighi, Ibrahim Ramez Chamas, Bhushan Shanti Asuri, Dongwon Seo
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Publication number: 20200169266Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Inventors: Shahin MEHDIZAD TALEIE, Behnam SEDIGHI, Dongwon SEO, Parisa MAHMOUDIDARYAN, Bhushan Shanti ASURI, Sang-June PARK, Shrenik PATEL
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Patent number: 10663572Abstract: Certain aspects of the present disclosure generally relate to a programmable multi-mode digital-to-analog converter (DAC) for generating a frequency-modulated signal. For example, certain aspects provide a circuit for sweeping a frequency of an output signal. The circuit generally includes a DAC having an input coupled to an input path of the circuit and an output coupled to an output path of the circuit, a first mixer selectively incorporated in the input path coupled to the input of the DAC, and a second mixer selectively incorporated in the output path coupled to the output of the DAC.Type: GrantFiled: June 19, 2018Date of Patent: May 26, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Chen Jiang, Dongwon Seo, Udara Fernando, Shrenik Patel, Roberto Rimini, Anant Gupta
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Patent number: 10666285Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.Type: GrantFiled: November 28, 2018Date of Patent: May 26, 2020Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Behnam Sedighi, Dongwon Seo, Parisa Mahmoudidaryan, Bhushan Shanti Asuri, Sang-June Park, Shrenik Patel
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Patent number: 10651957Abstract: An apparatus is disclosed for proximity detection using a hybrid-transceiver. In an example aspect, the apparatus includes a hybrid transceiver coupled to a first antenna and a second antenna. The hybrid transceiver is configured to generate, in a digital domain, a digital baseband radar signal. The hybrid transceiver is also configured to transmit, via the first antenna, a radio-frequency transmit signal that is derived from the digital baseband radar signal. Via the second antenna, the hybrid transceiver is configured to receive a radio-frequency receive signal, which includes a portion of the radio-frequency transmit signal that is reflected by an object. In an analog domain, the hybrid transceiver is configured to generate an analog receive signal that includes a beat frequency, which is indicative of a frequency offset between the radio-frequency transmit signal and the radio-frequency receive signal. The analog receive signal is derived from the radio-frequency receive signal.Type: GrantFiled: May 6, 2019Date of Patent: May 12, 2020Assignee: QUALCOMM IncorporatedInventors: Roberto Rimini, Udara Fernando, Shahin Mehdizad Taleie
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Publication number: 20200099389Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.Type: ApplicationFiled: March 28, 2019Publication date: March 26, 2020Inventors: Eunyung Sung, Nitz Saputra, Behnam Sedighi, Ashok Swaminathan, Honghao Ji, Shahin Mehdizad Taleie, Dongwon Seo
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Patent number: 10516412Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.Type: GrantFiled: September 21, 2018Date of Patent: December 24, 2019Assignee: QUALCOMM IncorporatedInventors: Shahin Mehdizad Taleie, Ashok Swaminathan, Sudharsan Kanagaraj, Negar Rashidi, Siyu Yang, Behnam Sedighi, Honghao Ji, Jaswinder Singh, Andrew Weil, Dongwon Seo, Xilin Liu
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Publication number: 20190383924Abstract: Certain aspects of the present disclosure generally relate to a programmable multi-mode digital-to-analog converter (DAC) for generating a frequency-modulated signal. For example, certain aspects provide a circuit for sweeping a frequency of an output signal. The circuit generally includes a DAC having an input coupled to an input path of the circuit and an output coupled to an output path of the circuit, a first mixer selectively incorporated in the input path coupled to the input of the DAC, and a second mixer selectively incorporated in the output path coupled to the output of the DAC.Type: ApplicationFiled: June 19, 2018Publication date: December 19, 2019Inventors: Shahin MEHDIZAD TALEIE, Chen JIANG, Dongwon SEO, Udara FERNANDO, Shrenik PATEL, Roberto RIMINI, Anant GUPTA
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Patent number: 10454509Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.Type: GrantFiled: April 25, 2018Date of Patent: October 22, 2019Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Krishnaswamy Thiagarajan, Ashok Swaminathan, Shahin Mehdizad Taleie, Yen-Wei Chang, Vinod Panikkath, Sameer Vasantlal Vora, Ayush Mittal, Tonmoy Biswas, Sy-Chyuan Hwu, Zhilong Tang, Ibrahim Chamas, Ping Wing Lai, Behnam Sedighi, Dongwon Seo, Nitz Saputra