Abstract: Disclosed are techniques that can be used in a semiconductor chip to determine performance such as timing performance. Among other features, supply voltages and clock rates may be adjusted to accommodate the operating temperature and to compensate for the processing variations that occurred when that chip was produced, or may occur as the chip is used. The techniques include determining a series of variables that affect performance, determining the sensitivity of timing paths in the circuit to each variable, duplicating the most sensitive paths. A novel sensor circuit is produced that includes the sensitive paths, which can be used to determine when the chip is performing as required and when it is not, and adjusting one or more supply voltages and/or clock rates in a static or real time manner when the circuit is not performing as required.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: Methods, devices and systems are described that relate to an energy optimal computing control system, where clock rates and supply voltage are control knobs to adjust the total energy consumption of an electronic circuit. An ultra-wide voltage range, such as from near-threshold voltage to the device maximum voltage, is used to maximize the performance and to minimize the energy consumption. One example device includes a processor that receives or determines the temperature of the electronic circuit, and determines the optimum voltage levels and clock rates for the electronic circuit at the operating temperature. This information is provided to a voltage regulator and a clock generator to adjust the supply voltage and clock frequency accordingly.

Abstract: Disclosed are techniques that can be used in a semiconductor chip to determine performance such as timing performance. Among other features, supply voltages and clock rates may be adjusted to accommodate the operating temperature and to compensate for the processing variations that occurred when that chip was produced, or may occur as the chip is used. The techniques include determining a series of variables that affect performance, determining the sensitivity of timing paths in the circuit to each variable, duplicating the most sensitive paths. A novel sensor circuit is produced that includes the sensitive paths, which can be used to determine when the chip is performing as required and when it is not, and adjusting one or more supply voltages and/or clock rates in a static or real time manner when the circuit is not performing as required.

Abstract: Methods, devices and systems are described that relate to an energy optimal computing control system, where clock rates and supply voltage are control knobs to adjust the total energy consumption of an electronic circuit. An ultra-wide voltage range, such as from near-threshold voltage to the device maximum voltage, is used to maximize the performance and to minimize the energy consumption. One example device includes a processor that receives or determines the temperature of the electronic circuit, and determines the optimum voltage levels and clock rates for the electronic circuit at the operating temperature. This information is provided to a voltage regulator and a clock generator to adjust the supply voltage and clock frequency accordingly.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

Abstract: A duty cycle adjustment apparatus includes a duty cycle adjustment determination module configured to determine an adjustment to a duty cycle of a clock signal, and includes a clock delay module configured to receive the clock signal, to delay the clock signal through first and second delay stage modules (with a first and a second plurality of delay paths, respectively) based on the duty cycle adjustment determined by the duty cycle adjustment determination module, and to output the delayed clock signal. The second plurality of delay paths have a greater delay difference between each of the corresponding delay paths than the first plurality of delay paths. The apparatus further includes a duty cycle adjustment module configured to receive the clock signal and the delayed clock signal, to adjust the duty cycle of the clock signal based on the delayed clock signal, and to output a duty cycle adjusted clock signal.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate.

Abstract: A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.