Patents by Inventor Shahin Tajik

Shahin Tajik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230401342
    Abstract: A method for detecting physical attacks on a computing device includes embedding a sensor or FPGA (Field Programmable Gate Array) on a circuit board for gathering a frequency response of a power distribution network providing power to the circuit board. During operation of the circuit board, the sensor identifies and gathers a frequency response suspected of resulting from a tamper effort, and compares the identified frequency response to a frequency response of tempering events. Based on the comparison, a determination of tampering is made.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 14, 2023
    Inventors: Shahin Tajik, Patrick Schaumont, Tahoura Mosavirik
  • Patent number: 11799673
    Abstract: Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 24, 2023
    Assignees: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED, TECHNISCHE UNIVERSITAET BERLIN
    Inventors: Fatemeh Ganji, Shahin Tajik, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor
  • Publication number: 20230179434
    Abstract: Combined physical unclonable function (PUFs); methods, apparatuses, systems, and computer program products for enrolling combined PUFs; and methods, apparatuses, systems, and computer program products for authenticating a device physically associated with a combined PUF are described. In an example embodiment, a combined PUF includes a plurality of PUFs and one or more logic gates. Each PUF includes a plurality of stages and an arbiter configured to generate a single PUF response based on response portions generated by the plurality of stages. The one or more logic gates are configured to combine the single PUF response for each of the plurality of PUFs in accordance with a combination function to provide a combined response.
    Type: Application
    Filed: April 7, 2020
    Publication date: June 8, 2023
    Applicant: Technische Universitaet Berlin
    Inventors: Fatemeh Ganji, Shahin Tajik, Jean-Pierre Seifert, Domenic Forte, Mark M. Tehranipoor
  • Publication number: 20210286905
    Abstract: A method includes in part, generating an electro-optical frequency map (EOFM) of an active layer of an integrated circuit (IC), retrieving a reference map of the IC, comparing the EOFM of the IC with the reference map to determine whether there is a match between an intensity of an identified region in the EOFM map and an intensity of a corresponding region of the reference map, and detecting one or more hardware trojans in the IC if there is no match. The reference map may be associated with a layout of an IC known not to include hardware trojans. The reference map also may be a second EOFM associated with the IC. Alternatively, the reference map may be generated by applying power to the IC, and applying a clock signal to the IC.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Inventors: Mark M. Tehranipoor, Andrew Stern, Shahin Tajik, Farimah Farahmandi