Patents by Inventor Shahnaz P. Chowdhury-Nagle

Shahnaz P. Chowdhury-Nagle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7706207
    Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: April 27, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas W. Liston, Shahnaz P. Chowdhury-Nagle, Perry H. Pelley, III
  • Publication number: 20090021990
    Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
    Type: Application
    Filed: September 12, 2008
    Publication date: January 22, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Thomas W. Liston, Shahnaz P. Chowdhury-Nagle, Perry H. Pelley, III
  • Patent number: 7440354
    Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: October 21, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas W. Liston, Shahnaz P. Chowdhury-Nagle, Perry H. Pelley, III