Patents by Inventor Shahram Nikoukary

Shahram Nikoukary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149521
    Abstract: An electronic device includes an electrically insulating substrate, a digital signal processor, and a photonics assembly. The electrically insulating substrate includes a main body. The digital signal processor is disposed on a first surface of the electrically insulating substrate and is arranged relative to the electrically insulating substrate such that a portion of the digital signal processor extends beyond the main body of the electrically insulating substrate. The photonics assembly is disposed adjacent to the electrically insulating substrate and electrically coupled to the digital signal processor.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 8, 2025
    Applicant: MaxLinear, Inc.
    Inventors: Abdelkrim El Amili, Shahram Nikoukary, Curtis Ling
  • Patent number: 12237258
    Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 25, 2025
    Assignee: Rambus Inc.
    Inventors: Shahram Nikoukary, Dongwoo Hong, Jonghyun Cho
  • Patent number: 12211583
    Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 28, 2025
    Assignee: Rambus Inc.
    Inventors: Torsten Partsch, Shahram Nikoukary, Catherine Chen
  • Patent number: 12087681
    Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: September 10, 2024
    Assignee: Rambus Inc.
    Inventors: Shahram Nikoukary, Jonghyun Cho, Nitin Juneja, Ming Li
  • Patent number: 12027197
    Abstract: A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 2, 2024
    Assignee: Rambus Inc.
    Inventors: Shahram Nikoukary, Jonghyun Cho, Anand Jai, Pradeep Batra, Lei Luo
  • Publication number: 20230298642
    Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.
    Type: Application
    Filed: August 24, 2021
    Publication date: September 21, 2023
    Inventors: Torsten Partsch, Shahram Nikoukary, Catherine Chen
  • Patent number: 11742277
    Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 29, 2023
    Assignee: Rambus Inc.
    Inventors: Shahram Nikoukary, Jonghyun Cho, Nitin Juneja, Ming Li
  • Publication number: 20220319980
    Abstract: The embodiments herein are directed to technologies for crosstalk cancellation structures. One semiconductor package includes conductive metal layers separated by insulating layers, the conductive metal layers for routing signals between external package terminals and pads on an integrated circuit device. Signal lines formed in the conductive metal layers have electrode structure (capacitor electrode-like structures) formed for at least adjacent signaling lines of the package terminals. Two of the electrode structures from the adjacent signaling lines are formed opposite each other on different metal layers.
    Type: Application
    Filed: April 30, 2020
    Publication date: October 6, 2022
    Inventors: Shahram Nikoukary, Dongwoo Hong, Jonghyun Cho
  • Publication number: 20080272468
    Abstract: An integrated circuit package for blocking electromagnetic interference includes a top layer formed in a package substrate. A first plurality of via groups is formed in the top layer surrounding an area on the top layer for an integrated circuit die. At least one lower layer is formed in the package substrate. A lower via group is formed in the lower layer below each of the first plurality of via groups, respectively. An electrical connection is formed in the lower layer between each lower via group and the first plurality of via groups, respectively. A ground connection is formed in the integrated circuit package for each lower via group to connect each lower via group to an electrical ground to block electromagnetic interference.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 6, 2008
    Inventors: Farshad Ghaghahi, Shahram Nikoukary, Halford Kokichi Tome
  • Publication number: 20060284310
    Abstract: A printed circuit board with an electrically conductive bonding pad disposed on an outer surface of the printed circuit board. The bonding pad has a bonding pad perimeter at immediately bounding edges of the bonding pad. An electrically conductive via directly electrically contacts the bonding pad, and is disposed within the printed circuit board relative to the bonding pad. The via has a via perimeter at immediately bounding edges of the via. The via perimeter overlaps the pad perimeter such that a portion of the via perimeter is within the pad perimeter and a portion of the via perimeter is outside the pad perimeter. In various embodiments, the bonding pad is a ball bonding pad.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Jeffrey Hall, Shahram Nikoukary