Patents by Inventor Shahriar Moinian

Shahriar Moinian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8464202
    Abstract: A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 11, 2013
    Assignee: LSI Corporation
    Inventors: Shawn Boshart, Shahriar Moinian, Joshua Williams, Hong-Ha Vuong
  • Publication number: 20120304140
    Abstract: A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Inventors: Shawn Boshart, Shahriar Moinian, Joshua Williams, Hong-ha Vuong
  • Patent number: 8283713
    Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: October 9, 2012
    Assignee: LSI Corporation
    Inventors: John G. Jansen, Chi-Yi Kao, Ce Chen, Shahriar Moinian
  • Patent number: 8143696
    Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: March 27, 2012
    Assignee: Agere Systems Inc.
    Inventors: Weiwei Mao, Shahriar Moinian, Kenneth Wade Paist, William B. Wilson
  • Publication number: 20110298026
    Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.
    Type: Application
    Filed: March 14, 2011
    Publication date: December 8, 2011
    Applicant: LSI Corporation
    Inventors: John G. Jansen, Chi-Yi Kao, Ce Chen, Shahriar Moinian
  • Publication number: 20100314713
    Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
    Type: Application
    Filed: March 18, 2009
    Publication date: December 16, 2010
    Inventors: Weiwei Mao, Shahriar Moinian, Kenneth Wade Paist, William B. Wilson
  • Patent number: 7847666
    Abstract: An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 7, 2010
    Assignee: Agere Systems Inc.
    Inventors: Shahriar Moinian, John E. Scoggins
  • Publication number: 20100244276
    Abstract: An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 30, 2010
    Applicant: LSI Corporation
    Inventors: Jeffrey P. Burleson, Shahriar Moinian, John Osenbach, Jayanthi Pallinti
  • Patent number: 7480874
    Abstract: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: January 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Kausar Banoo, Seung H. Kang, Shahriar Moinian, Blane A. Musser, John A. Pantone
  • Publication number: 20080074229
    Abstract: An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Shahriar Moinian, John E. Scoggins
  • Patent number: 7345354
    Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: March 18, 2008
    Assignee: Agere Systems Inc.
    Inventors: Debra Johnson, Shye Shapira, Shahriar Moinian
  • Publication number: 20070033555
    Abstract: Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 8, 2007
    Inventors: Kausar Banoo, Seung Kang, Shahriar Moinian, Blane Musser, John Pantone
  • Patent number: 7174532
    Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: February 6, 2007
    Assignee: Agere Systems, Inc.
    Inventors: James D. Chlipala, Shahriar Moinian
  • Publication number: 20060107243
    Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Applicant: Agere Systems Inc.
    Inventors: James Chlipala, Shahriar Moinian
  • Publication number: 20050023645
    Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 3, 2005
    Applicant: Agere Systems Inc.
    Inventors: Shye Shapira, Debra Johnson, Shahriar Moinian
  • Publication number: 20040245604
    Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Applicant: Agere Systems Inc.
    Inventors: Shye Shapira, Debra Johnson, Shahriar Moinian
  • Patent number: 6825089
    Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: November 30, 2004
    Assignee: Agere Systems Inc.
    Inventors: Shye Shapira, Debra Johnson, Shahriar Moinian
  • Patent number: 6657281
    Abstract: The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: December 2, 2003
    Assignee: Agere Systems Inc.
    Inventors: Yih-Feng Chyan, Chunchieh Huang, Chung Wai Leung, Yi Ma, Shahriar Moinian
  • Patent number: 6395611
    Abstract: An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: May 28, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Nathan Belk, William Thomas Cochran, Michel Ranjit Frei, David Clayton Goldthorp, Shahriar Moinian, Kwok K. Ng, Mark Richard Pinto, Ya-Hong Xie