Patents by Inventor Shahriar Rabii
Shahriar Rabii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11250537Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.Type: GrantFiled: November 25, 2019Date of Patent: February 15, 2022Assignee: Google LLCInventors: Fabrizio Basso, Edward Chang, Daniel Finchelstein, Timothy Knight, William Mark, Albert Meixner, Shahriar Rabii, Jason Redgrave, Masumi Reynders, Ofer Shacham, Don Stark, Michelle Tomasko
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Publication number: 20200167890Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.Type: ApplicationFiled: November 25, 2019Publication date: May 28, 2020Inventors: Fabrizio Basso, Edward Chang, Daniel Finchelstein, Timothy Knight, William Mark, Albert Meixner, Shahriar Rabii, Jason Redgrave, Masumi Reynders, Ofer Shacham, Don Stark, Michelle Tomasko
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Patent number: 10489878Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.Type: GrantFiled: May 15, 2017Date of Patent: November 26, 2019Assignee: Google LLCInventors: Fabrizio Basso, Edward Chang, Daniel Finchelstein, Timothy Knight, William Mark, Albert Meixner, Shahriar Rabii, Jason Redgrave, Masumi Reynders, Ofer Shacham, Don Stark, Michelle Tomasko
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Publication number: 20180330466Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.Type: ApplicationFiled: May 15, 2017Publication date: November 15, 2018Inventors: Fabrizio Basso, Edward Chang, Daniel Finchelstein, Timothy Knight, William Mark, Albert Meixner, Shahriar Rabii, Jason Redgrave, Masumi Reynders, Ofer Shacham, Don Stark, Michelle Tomasko
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Patent number: 9484856Abstract: A modulated signal based on a low-precision, fast startup oscillator is provided to a circuit with a high-precision, slow startup oscillator. The frequency of the modulated signal ranges around the characteristic or resonant frequency of the high precision oscillator without using feedback from the high precision oscillator circuit. An implementation can include one or more variable gain circuits that can be adjusted based on an amplitude threshold in relation to the output signal of the high precision oscillator circuit.Type: GrantFiled: January 10, 2014Date of Patent: November 1, 2016Assignee: GOOGLE INC.Inventors: Clemenz Portmann, Cheng-Yi Andrew Lin, Shahriar Rabii
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Patent number: 9343377Abstract: A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit formed in a destroyable circuitry area on the substrate; testing at least one operational aspect of the device circuitry using the destroyable circuit; and destroying the destroyable circuit subsequent to testing the at least one operational aspect of the device circuitry.Type: GrantFiled: January 8, 2015Date of Patent: May 17, 2016Assignee: GOOGLE INC.Inventors: Andy Yang, Benjamin Iver Gribstad, Don Stark, Shahriar Rabii, Srenik Mehta
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Patent number: 9171642Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: GrantFiled: May 23, 2014Date of Patent: October 27, 2015Assignee: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Publication number: 20150200625Abstract: A modulated signal based on a low-precision, fast startup oscillator is provided to a circuit with a high-precision, slow startup oscillator. The frequency of the modulated signal ranges around the characteristic or resonant frequency of the high precision oscillator without using feedback from the high precision oscillator circuit. An implementation can include one or more variable gain circuits that can be adjusted based on an amplitude threshold in relation to the output signal of the high precision oscillator circuit.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: GOOGLE INC.Inventors: Clemenz Portmann, Cheng-Yi Andrew Lin, Shahriar Rabii
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Publication number: 20140253177Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Patent number: 8779953Abstract: A method and device for testing a digital-to-analog converter is provided. The method may include configuring a decoder to address an individual unit cell of a plurality of unit cells of a digital-to-analog converter. The configured decoder may select a particular unit cell of the plurality of unit cells for testing. The selected unit cell may have digital and analog circuitry. A bias current of the selected unit cell may be increased. The increased bias current of the selected unit cell may be greater during the testing than during normal operation. A test logic signal may be applied to the selected unit cell. In response to the test logic signal, an output signal may be output from the selected unit cell logic circuitry of the digital-to-analog converter. A device may include logic circuitry configured to select an individual unit cell for testing and a current generating circuitry.Type: GrantFiled: July 31, 2013Date of Patent: July 15, 2014Assignee: Google Inc.Inventors: Clemenz Portmann, Shahriar Rabii, Donald Charles Stark
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Patent number: 8766669Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: GrantFiled: September 10, 2012Date of Patent: July 1, 2014Assignee: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Patent number: 8369369Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.Type: GrantFiled: January 10, 2011Date of Patent: February 5, 2013Assignee: NetLogic Microsystems, Inc.Inventors: Stefanos Sidiropoulos, Shwetabh Verma, Shahriar Rabii
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Publication number: 20110103417Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Inventors: Stefanos Sidiropoulos, Shwetabh Verma, Shahriar Rabii
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Patent number: 7885300Abstract: A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device.Type: GrantFiled: March 2, 2006Date of Patent: February 8, 2011Assignee: NetLogic Microsystems, IncInventors: Stefanos Sidiropoulos, Shwetabh Verma, Shahriar Rabii
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Patent number: 7065327Abstract: A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.Type: GrantFiled: September 10, 1999Date of Patent: June 20, 2006Assignee: Intel CorporationInventors: Donald Evan Macnally, Thomas B. Cho, Shahriar Rabii, Srenik Suresh Mehta, Christopher Donald Nilson, Michael Peter Mack, Laurence Marguerite Plouvier, Menno Marringa, Eric S. Dukatz
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Patent number: 6744826Abstract: An AGC window detector that senses the sum of an in-phase (I) and a quadrature (Q) peak-to-peak signal swing and compares the signal to a reference voltage for producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the AGC circuits in the I/Q path of a wireless receiver. The signals Imax, Imin, Qmax and Qmin are the positive and negative peak values of the in-phase and the quadrature waveforms, respectively. They are generated by a peak detector. Thus the differential in-phase and the differential quadrature amplitudes are Imax−Imin and Qmax−Qmin,, respectively. A resulting differential in-phase signal is added to a resulting differential quadrature signal by the detector and compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages.Type: GrantFiled: March 10, 1999Date of Patent: June 1, 2004Assignee: Intel CorporationInventor: Shahriar Rabii
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Publication number: 20030091126Abstract: An AGC window detector that senses the sum of an in-phase (I) and a quadrature (Q) peak-to-peak signal swing and compares the signal to a reference voltage for producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the AGC circuits in the I/Q path of a wireless receiver. The signals Imax, Imin, Qmax and Qmin are the positive and negative peak values of the in-phase and the quadrature waveforms, respectively. They are generated by a peak detector. Thus the differential in-phase and the differential quadrature amplitudes are Imax−Imin and Qmax−Qmin,, respectively. A resulting differential in-phase signal is added to a resulting differential quadrature signal by the detector and compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages.Type: ApplicationFiled: March 10, 1999Publication date: May 15, 2003Inventor: SHAHRIAR RABII
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Patent number: 6469547Abstract: An offset window detector that senses the sum of two signals and compares the result to a reference voltage for attenuating an offset voltage and producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the offset circuits in the I/Q path of a wireless receiver. The maximum input signal and the minimum input signal are the positive and negative peak values of the in-phase or the quadrature signal paths. They are generated by a peak detector. The offset signal can be estimated by the addition of the maximum input signal with the minimum input signal. This resulting offset signal is compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages. A reference voltage generator creates the desired voltages within a desired tolerance.Type: GrantFiled: December 10, 1998Date of Patent: October 22, 2002Assignee: Level One Communications, Inc.Inventor: Shahriar Rabii
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Patent number: 6313685Abstract: An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity to produce a charge signal. An accumulation of the charge signal on a plurality of storage components is used to reduce the offset component of the output signal and simultaneously inducing an integrator leak. A positive and negative components of the input signals are combined with a negative and positive offset components of the part of the output signal, respectively. The method liner includes modifying a positive and negative components of an in-phase and a quadrature signal. A reset signal may be provided to erase a plurality of memory locations. A gating scheme may be used to provide a predetermined signal to produce a two-phase, non-overlapping signal.Type: GrantFiled: April 5, 2000Date of Patent: November 6, 2001Assignee: Level One Communications, Inc.Inventor: Shahriar Rabii
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Patent number: 6304136Abstract: An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadrature outputs of a receiver, which have been oversampled by a predetermined factor with respect to the data rate. The demodulator circuit differentiates the in-phase and the quadrature input signal by computing the difference between the current signal value and the signal value delayed by one clock period. The differentiated values of the in-phase and the quadrature signals may be changed based on the sign of the quadrature and the in-phase signals respectively to produce modified values of the differentiated in-phase and quadrature signals.Type: GrantFiled: March 3, 1999Date of Patent: October 16, 2001Assignee: Level One Communications, Inc.Inventor: Shahriar Rabii