Patents by Inventor Shahriar S. Ahmed

Shahriar S. Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6458667
    Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Patent number: 6384457
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: May 7, 2002
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Patent number: 6297104
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: October 2, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Publication number: 20010013628
    Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.
    Type: Application
    Filed: May 3, 1999
    Publication date: August 16, 2001
    Inventors: SUNIT TYAGI, SHAHRIAR S. AHMED
  • Patent number: 6177705
    Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: January 23, 2001
    Assignee: Intel Corporation
    Inventors: Sunit Tyagi, Shahriar S. Ahmed
  • Patent number: 6020244
    Abstract: An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: Scott E. Thompson, Paul A. Packan, Tahir Ghani, Mark Stettler, Shahriar S. Ahmed, Mark T. Bohr
  • Patent number: 5434093
    Abstract: A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.
    Type: Grant
    Filed: August 10, 1994
    Date of Patent: July 18, 1995
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Chan-Hong Chern, Shahriar S. Ahmed, Robert F. Hainsey, Robert J. Stoner, Todd E. Wilke, Leopoldo D. Yau