Abstract: In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

Abstract: An apparatus and a system, as well as a method and article, may operate to compare a circuit operational condition with a specified condition, to record an out-of-specification condition, and to determine some specified number of recorded out-of-specification conditions.

Abstract: In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

Abstract: An apparatus and a system, as well as a method and article, may operate to compare a circuit operational condition with a specified condition, to record an out-of-specification condition, and to determine some specified number of recorded out-of-specification conditions.

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Abstract: A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a first size are accessed via a page directory entry and a corresponding page table entry. The page directory entry stores a base physical address for a corresponding page table and control bits indicating permissions. The page table entry stores a base physical address of the page in memory. In one embodiment, the page table entry inherits permissions from the page directory entry. Pages of a second size are accessed via a page directory entry that stores a base physical address of the page and control bits indicating permissions associated with the page. In another embodiment, entries to the page directory table and the page table are 4-bytes in size and provide paging for memory up to 1.1 Terabytes in size.

Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.