Patents by Inventor Shahrukh A. Khan

Shahrukh A. Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220215325
    Abstract: An embodiment includes determining if a new incident report of a new incident matches any resolved incident reports associated with resolved incidents. The embodiment performs a first classification operation on the new incident report to determine if the new incident report is likely to be similar to any resolved incident reports associated with resolved incidents. The embodiment also performs a second classification operation on the new incident report to generate a ranked list of changes that are likely to be similar to the new incident report. The embodiment outputs the ranked list of changes to an incident manager for evaluation, then receives an input representative of a selected change from among the ranked list of changes responsible for causing the new incident. The embodiment revises the new incident report to include a reference to the selected change.
    Type: Application
    Filed: February 19, 2021
    Publication date: July 7, 2022
    Applicant: Kyndryl, Inc.
    Inventors: Omar Odibat, Sanjana Sahayaraj, Shahrukh Khan, Alexandre Francisco Da Silva, Nadeem Malik, Muhammad Faisal
  • Patent number: 9806161
    Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shahrukh A. Khan, Unoh Kwon, Shahab Siddiqui, Sean M. Polvino, Joseph F. Shepard, Jr.
  • Publication number: 20170294519
    Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Shahrukh A. Khan, Unoh Kwon, Shahab Siddiqui, Sean M. Polvino, Joseph F. Shepard, JR.
  • Patent number: 9748235
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Patent number: 9741581
    Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunit S. Mahajan, Parul Dhagat, Anne C. Friedman, Timothy A. Brunner, Shahrukh A. Khan
  • Publication number: 20170221889
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Publication number: 20170200614
    Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Inventors: Sunit S. Mahajan, Parul Dhagat, Anne C. Friedman, Timothy A. Brunner, Shahrukh A. Khan
  • Patent number: 9685334
    Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 20, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yue Ke, Mohammad Hasanuzzaman, Benjamin G. Moser, Shahrukh A. Khan, Sean M. Polvino
  • Publication number: 20170170016
    Abstract: Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Woo-Hyeong Lee, Jujin An, Shahrukh A. Khan, Rosa A. Orozco-Teran, Oluwafemi O. Ogunsola, William K. Henson, Scott R. Stiffler