Abstract: A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.

Abstract: Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.

Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.

Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.

Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.

Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract: Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.

Abstract: Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.

Abstract: In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point.