Patents by Inventor Shai Cohen
Shai Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220260630Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: ApplicationFiled: March 24, 2022Publication date: August 18, 2022Inventors: Eyal FAYNEH, Edi SHMUELI, Alexander BURLAK, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Shai COHEN, Guy REDLER
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Patent number: 11408932Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.Type: GrantFiled: January 8, 2019Date of Patent: August 9, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Inbar Weintrob, Evelyn Landman, Yahel David, Shai Cohen, Guy Redler
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Patent number: 11391771Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.Type: GrantFiled: November 22, 2018Date of Patent: July 19, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Shai Cohen, Evelyn Landman, Yahel David, Inbar Weintrob
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Patent number: 11385282Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: November 15, 2018Date of Patent: July 12, 2022Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Publication number: 20220156206Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Eyal FAYNEH, Evelyn LANDMAN, Shai COHEN, Guy REDLER, Inbar WEINTROB
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Patent number: 11275700Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: August 10, 2020Date of Patent: March 15, 2022Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Publication number: 20220012395Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Patent number: 11132485Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: GrantFiled: June 19, 2019Date of Patent: September 28, 2021Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yair Talker, Eyal Fayneh, Yahel David, Shai Cohen, Inbar Weintrob
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Publication number: 20210173007Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: April 16, 2019Publication date: June 10, 2021Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Publication number: 20210165941Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: June 19, 2019Publication date: June 3, 2021Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Publication number: 20210068465Abstract: An e-vaping device includes a liquid storage portion for storing an e-liquid; a memory device storing cartomizer information; a vaporizer including a heating element, the vaporizer being in fluid communication with the liquid storage portion and configured to vaporize e-liquid stored in the liquid storage portion; a power supply configured to provide power to the vaporizer; a controller configured to control provision of power to the vaporizer based on the cartomizer information; and a switching architecture configured to selectively prevent a flow of current through the heating element, when the memory device sends data to the controller.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Applicant: Altria Client Services LLCInventors: Alex MALAMUD, Shai COHEN, Amit DAR
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Patent number: 10888122Abstract: An e-vaping device includes a liquid storage portion for storing an e-liquid; a memory device storing cartomizer information; a vaporizer including a heating element, the vaporizer being in fluid communication with the liquid storage portion and configured to vaporize e-liquid stored in the liquid storage portion; a power supply configured to provide power to the vaporizer; a controller configured to control provision of power to the vaporizer based on the cartomizer information; and a switching architecture configured to selectively prevent a flow of current through the heating element, when the memory device sends data to the controller.Type: GrantFiled: May 24, 2018Date of Patent: January 12, 2021Assignee: ALTRIA CLIENT SERVICES LLCInventors: Alex Malamud, Shai Cohen, Amit Dar
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Publication number: 20200393506Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: November 15, 2018Publication date: December 17, 2020Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20200371972Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: Eyal FAYNEH, Evelyn LANDMAN, Shai COHEN, Guy REDLER, Inbar WEINTROB
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Publication number: 20200363468Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.Type: ApplicationFiled: November 22, 2018Publication date: November 19, 2020Inventors: Eyal FAYNEH, Shai COHEN, Evelyn LANDMAN, Yahel DAVID, Inbar WEINTROB
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Publication number: 20200333393Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.Type: ApplicationFiled: January 8, 2019Publication date: October 22, 2020Inventors: Eyal FAYNEH, Inbar WEINTROB, Evelyn LANDMAN, Yahel DAVID, Shai COHEN, Guy REDLER
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Patent number: 10756682Abstract: A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.Type: GrantFiled: February 2, 2020Date of Patent: August 25, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Hananel Faig, Shai Cohen, Liron Gantz
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Patent number: 10740262Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: December 30, 2019Date of Patent: August 11, 2020Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Publication number: 20200252032Abstract: A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.Type: ApplicationFiled: February 2, 2020Publication date: August 6, 2020Inventors: Hananel Faig, Shai Cohen, Liron Gantz
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Publication number: 20200210354Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: ApplicationFiled: December 30, 2019Publication date: July 2, 2020Inventors: Eyal FAYNEH, Evelyn LANDMAN, Shai COHEN, Guy REDLER, Inbar WEINTROB