Patents by Inventor Shai Eisen
Shai Eisen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170000349Abstract: The present invention provides for an apparatus, including: a lancing device; a cartridge; where the lancing device is configured to house the cartridge; where the cartridge is configured to house a plurality of test strips and a glucose monitoring apparatus; where the glucose monitoring apparatus is configured to determine a glucose test result from at least one test strip of the plurality of test strips.Type: ApplicationFiled: March 13, 2015Publication date: January 5, 2017Inventors: Liron HADAR, Erez RAPHAEL, Shai EISEN, Jonathan KANETY, Yoav TIKOCHINSKY, Haim KRIEF, Daniel DARST, Eric Jason KRAUSE
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Patent number: 7924628Abstract: A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).Type: GrantFiled: November 14, 2008Date of Patent: April 12, 2011Assignee: Spansion Israel LtdInventors: Kobi Danon, Shai Eisen, Marcelo Krygier
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Publication number: 20090122610Abstract: A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).Type: ApplicationFiled: November 14, 2008Publication date: May 14, 2009Inventors: Kobi Danon, Shai Eisen, Marcelo Krygier
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Patent number: 7468926Abstract: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.Type: GrantFiled: January 19, 2006Date of Patent: December 23, 2008Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Shai Eisen
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Patent number: 7369440Abstract: The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.Type: GrantFiled: January 19, 2006Date of Patent: May 6, 2008Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Shai Eisen
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Publication number: 20060181934Abstract: A method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array.Type: ApplicationFiled: January 19, 2006Publication date: August 17, 2006Applicant: Saifun Semiconductors, Ltd.Inventors: Assaf Shappir, Shai Eisen, Guy Cohen, Kobi Danon
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Publication number: 20060158938Abstract: The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.Type: ApplicationFiled: January 19, 2006Publication date: July 20, 2006Applicant: Saifun Semiconductors, Ltd.Inventors: Assaf Shappir, Shai Eisen
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Publication number: 20060158940Abstract: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.Type: ApplicationFiled: January 19, 2006Publication date: July 20, 2006Applicant: Saifun Semiconductors, Ltd.Inventors: Assaf Shappir, Shai Eisen
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Patent number: 6967896Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.Type: GrantFiled: January 30, 2003Date of Patent: November 22, 2005Assignee: Saifun Semiconductors LTDInventors: Shai Eisen, Roni Varkony, Mori Edan
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Patent number: 6842383Abstract: According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.Type: GrantFiled: January 30, 2003Date of Patent: January 11, 2005Assignee: Saifun Semiconductors Ltd.Inventors: Joseph S. Shor, Avri Harush, Shai Eisen
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Publication number: 20040153620Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Shai Eisen, Roni Varkony, Mori Edan
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Publication number: 20040151034Abstract: According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Joseph S. Shor, Avri Harush, Shai Eisen
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Patent number: 6636440Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.Type: GrantFiled: April 25, 2001Date of Patent: October 21, 2003Assignee: Saifun Semiconductors Ltd.Inventors: Eduardo Maayan, Ron Eliyahu, Shai Eisen, Boaz Eitan
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Publication number: 20020191465Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.Type: ApplicationFiled: April 25, 2001Publication date: December 19, 2002Inventors: Eduardo Maayan, Ron Eliyahu, Shai Eisen, Boaz Eitan