Patents by Inventor Shai Haimson

Shai Haimson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structures having adhesion promoting layer in cavities
    Patent number: 9159662
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close of the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • FILLING CAVITIES IN SEMICONDUCTOR STRUCTURES HAVING ADHESION PROMOTING LAYER IN THE CAVITIES
    Publication number: 20140299992
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close of the trench at the top during filling may be reduced in sonic embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Barrier layer for integrated circuit contacts
    Patent number: 8810033
    Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Avraham Rozenblat, Shai Haimson, Rotem Drori, Maor Rotlain, Dror Horvitz
  • Filling cavities in semiconductor structures having adhesion promoting layer in the cavities
    Patent number: 8772155
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • BARRIER LAYER FOR INTEGRATED CIRCUIT CONTACTS
    Publication number: 20130241066
    Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 19, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Avraham Rozenblat, Shai Haimson, Rotem Drori, Maor Rotlain, Dror Horvitz
  • Barrier layer for integrated circuit contacts
    Patent number: 8461043
    Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Avraham Rozenblat, Shai Haimson, Rotem Drori, Maor Rotlain, Dror Horvitz
  • Barrier Layer for Integrated Circuit Contacts
    Publication number: 20120256317
    Abstract: Plug contacts may be formed with barrier layers having thicknesses of less than 50 ? in some embodiments. In one embodiment, the barrier layer may be formed by the chemical vapor deposition of diborane, forming a boron layer between a metallic contact and the surrounding dielectric and between a metallic contact and the substrate and/or substrate contact. This boron layer may be substantially pure boron and boron silicide.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Inventors: Avraham Rozenblat, Shai Haimson, Rotem Drori, Maor Rotlain, Dror Horvitz
  • Filling Cavities in Semiconductor Structures
    Publication number: 20120126415
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 24, 2012
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Lithographic patterning for sub-90nm with a multi-layered carbon-based hardmask
    Patent number: 7803715
    Abstract: Multi-layered carbon-based hardmask and method to form the same. The multi-layered carbon-based hardmask includes at least top and bottom carbon-based hardmask layers having different refractive indexes. The top and bottom carbon-based hardmask layer thicknesses and refractive indexes are tuned so that the top carbon-based hardmask layer serves as an anti-reflective coating (ARC) layer.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: September 28, 2010
    Inventors: Shai Haimson, Gabe Schwartz, Michael Shifrin