Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Abstract: A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing the upper oxide layer and a portion of the nitride layer using an isotropic plasma enhanced etch, and then removing the remainder of the nitride layer and a portion of the lower oxide layer using an isotropic plasma enhanced etch, wherein the semiconductor wafer is not exposed through the lower oxide layer. The method can be used to form gate electrodes and diffusion bit liens in a fieldless array of non-volatile memory cells.

Abstract: A fieldless array of floating gate transistors is fabricated by forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate. A mask is formed over the ONO layer, the mask having openings that define a plurality of bit line regions of the floating gate transistors in the substrate. A first impurity is implanted into the bit line regions of the substrate, wherein the first impurity is implanted through the ONO layer, through the openings of the mask. The first impurity is implanted at various angles, such that the first impurity is implanted in the substrate at locations beneath the mask. The upper oxide and nitride layers of the ONO layer are subsequently etched through the mask openings. A second impurity is implanted in the substrate through the openings of the mask. The mask is removed, and the substrate is oxidized, thereby forming bit line oxide regions over the bit line regions, and floating gate structures.

Abstract: A method for etching an oxide-nitride-oxide (ONO) layer fabricated on a semiconductor wafer, the ONO layer including a lower oxide layer, a nitride layer located over the lower oxide layer, and an upper oxide layer located over the nitride layer. The method includes the steps of removing the upper oxide layer and a portion of the nitride layer using an isotropic plasma enhanced etch, and then removing the remainder of the nitride layer and a portion of the lower oxide layer using an isotropic plasma enhanced etch, wherein the semiconductor wafer is not exposed through the lower oxide layer. The method can be used to form gate electrodes and diffusion bit liens in a fieldless array of non-volatile memory cells.